View GP1020_1945078.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds3605-2.2 the GP1020 is a six-channel cmos digital correlator which has been designed to work with the gp1010 l1-channel down- converter or other integrated circuits, and may be used to acquire and track the gps c/a code or the glonass signals. for each of the six channels the GP1020 includes independ- ent digital down-conversion to baseband, c/a code generation, correlation, and accumulate-and-dump registers. the GP1020 interfaces with a microprocessor via a 16-bit data bus to control the acquisition and tracking processes using the various registers on the chip. features n six fully independent correlation channels n switchable to receive gps or glonass codes n input multiplexer for multiple gps front-ends C allows antenna diversity n input multiplexer for glonass multiple (separate channels) front-ends n digital interface compatible with most 16 or 32-bit microprocessors n fully compatible with gp1010 gps receiver front-end n sideways stackable to give multiples of six channels n 120-pin plastic quad flatpack n power dissipation less than 500mw applications n gps or glonass navigation systems n high integrity combined receivers n gps geodetic receivers n gps time reference ordering information the GP1020 is available in 120-pin quad flatpacks (gullwing formed leads) in both commercial (0 c to 1 70 c) and industrial ( 2 40 c to 1 85 c) grades. the ordering codes below are for standard screened devices. ordering codes GP1020 cg gpkr commercial - plastic 120-pin qfp (gp120) GP1020 ig gpkr industrial - plastic 120-pin qfp (gp120) gp 1020 91 120 61 90 1 30 31 60 gp120 fig 1 pin connections - top view absolute maximum ratings these are not the operating conditions, but are the absolute limits which if exceeded, even momentarily, may cause perma- nent damage. to ensure sustained correct operation the device should be used within the limits given under electrical character- istics. supply voltage (v dd ) from ground (v ss ): 2 03v to 1 60 v input voltage (any input pin): v ss 2 03v to v dd 1 03 v output voltage (any output pin): v ss 2 03v to v dd 1 03 v storage temperature: 2 55 c to 1 125 c related products description 3542mhz saw filter gps receiver front-end part dw9255 gp1010 datasheet reference ds3861 ds3076 GP1020 six-channel parallel correlator circuit for gps or glonass receivers february 1994
2 GP1020 typical gps receiver (fig. 2) all satellites use the same l1 frequency of 157542mhz, but different gold codes, so a single front-end may be used. to achieve better sky coverage it may be desirable to use more than one antenna, in which case separate front-ends will be needed. typical glonass receiver (fig. 3) each satellite will use a different ?l1? carrier frequency, in the range 16025625 to 1615500mhz, with 05625mhz spacing, but all with the same 511-bit spreading code. the normal method for receiving these signals is to use several front-ends, perha ps with the first lna and mixer common, but certainly with different final local oscillators and mixers. fig. 3 glonass receiver simplified block diagram fig. 2 gps receiver simplified block diagram GP1020 (master) sign 0 mag 0 sign 1 mag 1 optional second GP1020 (slave) v dd gnd masterreset sign 0 mag 0 sign 1 mag 1 v dd gnd masterreset data bus (16) addr bus (8) master / slave 1 5v master / slave v ss v ss slaveclk tic out tic in int out int in 1 5v decode decode microprocessor system master clk sample clk sign mag gp1010 & filter optional second gp1010 & filter cs cs multiple antennas to give wider sky coverage control 3 navigation solution v dd gnd master / slave v ss 1 5v GP1020 masterreset data bus (16) addr bus (8) decode microprocessor system oscillator frequency selection int out sample clk sign mag channel selection and adc sign mag channel selection and adc channel selection and adc sign mag channel selection and adc sign mag channel selection and adc sign mag channel selection and adc sign mag channel selection and adc frequency generator samp clk sign 0 mag 0 sign 1 mag 1 sign 2 mag 2 sign 3 mag 3 sign 4 mag 4 sign 5 mag 5 l-band down converter cs master clock glonass front-end filters, amplifiers and mixers control 3 navigation solution
GP1020 3 pin descriptions (see application notes, p. 41) all v ss and all v dd pins must be used in order to ensure reliable operation. several pins, such as satellite inputs 2 to 9 sign and magnitudes are also used for device testing, but only as a secondary function. description type register address, bit 7 register address, bit 8 master or slave mode select scan test mode select test clock select serial test data input master reset (active low) motorola (hi) or intel (lo) bus select chip select (active low) for bus ground positive supply bus control - see note 1 bus control - see note 1 test mode select 2 test mode select 1 test prn pattern magnitude o/p test prn pattern sign output satellite input 2, magnitude programmable interrupt timer clock positive supply ground interrupt out to microprocessor satellite input 2, sign satellite input 3, magnitude satellite input 3, sign satellite input 4, magnitude satellite input 4, sign satellite input 5, magnitude satellite input 5, sign satellite input 6, magnitude satellite input 6, sign satellite input 7, magnitude satellite input 7, sign satellite input 8, magnitude satellite input 8, sign satellite input 9, magnitude satellite input 9, sign satellite input 1, magnitude satellite input 1, sign ground positive supply satellite input 0, magnitude satellite input 0, sign sampling clock to down-converter positive supply 40mhz master clock ground bias for masterclk in 600mv ac-coupled mode ground positive supply ground sets 100/219khz to 100or 219khz pll lock status from down-converter bite control to down-converter i/p to monitor glonass front-end 20mhz clock from master to slave interrupt to slave to sync to master test clock 1 test clock 2 test clock 3 test clock 4 test clock 5 test clock 6 test clock 7 test clock 8 pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 signal name a7 a8 master/ slave tscan tcks tdi1 master reset mot/ intel cs v ss v dd wen rw tms2 tms1 tmag tsign mag2 100/219khz v dd v ss intout sign2 mag3 sign3 mag4 sign4 mag5 sign5 mag6 sign6 mag7 sign7 mag8 sign8 mag9 sign9 mag1 sign1 v ss v dd mag0 sign0 sampclk v dd masterclk v ss bias v ss v dd v ss clksel plllockin bitecntl glonassbit slaveclk intin tck1 tck2 tck3 tck4 tck5 tck6 tck7 tck8 i i i i i i i i i 2 1 i i i i o o i/o o 1 2 o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 2 1 i i o 1 i 2 o 2 1 2 i i o i i/o i i/o i/o i/o i/o i/o i/o i/o i tic input to slave tic output from master data bus, bit 0 data bus, bit 1 ground positive supply data bus, bit 2 data bus, bit 3 one pulse per second output real time clock interrupt input timemark line driver feedback timemark line driver feedback data bus, bit 4 data bus, bit 5 positive supply ground data bus, bit 6 data bus, bit 7 bus timing mode - see note 2 test structure - see note 3 test structure - see note 3 boundary scan output boundary scan clock boundary scan reset test structure - see note 3 boundary scan control boundary scan input timemark line driver feedback serial test data output 7 on/off control for lna by gp1010 serial test data output 6 serial test data output 5 data bus, bit 8 data bus, bit 9 ground positive supply data bus, bit 10 data bus, bit 11 serial test data output 4 serial test data output 3 serial test data output 2 serial test data output 1 data bus, bit 12 data bus, bit 13 positive supply ground data bus, bit 14 data bus, bit 15 address latch enable, bus control register address, bit 1 (lsb) register address, bit 2 register address, bit 3 register address, bit 4 register address, bit 5 register address, bit 6 pin no. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 signal name ticin ticout d0 d1 v ss v dd d2 d3 time mark rtcint markfb1 markfb2 d4 d5 v dd v ss d6 d7 wprog nanda nandb tdo tck trst nandop tms tdi markfb3 tdo7 discop tdo6 tdo5 d8 d9 v ss v dd d10 d11 tdo4 tdo3 tdo2 tdo1 d12 d13 v dd v ss d14 d15 ale a1 a2 a3 a4 a5 a6 description type i o i/o i/o 2 1 i/o i/o o i i i i/o i/o 1 2 i/o i/o i i i o i i o i i i o o o o i/o i/o 2 1 i/o i/o o o o o i/o i/o 1 2 i/o i/o i i i i i i i mot/ intel 1 1 0 0 wen 1 1 1 0 rw 0 1 0 1 mode motorola motorola intel intel function write read read write note 1. the functions of rw and wen pins depend on whether the GP1020 is in motorolaa (mot/ intel = ?1?) or intela mode (mot/ intel = ?0?). in motorola mode, wen is an enable (active high) and rw is read/ write select (?1? = read). in intel mode rw is read, active low, and wen is write, also active low. note 2. wprog is used to modify the timing of bus operations; when it is held high the internal write signal is ored with ale to allow time for the internal address lines to stabilise; when it is held low there is no delay added to write. note 3. nandop (pin 90) is the output of a spare gate with inputs on nanda (pin 85) and nandb (pin 86).
4 GP1020 ma v v k w v v k w v v m a v v k w v v k w mv v v v v v v m a v v m a v v m a 75 75 1 75 75 v dd 2 05 02 v dd 2 05 02 v dd 2 05 02 v dd 2 05 02 v dd 2 05 02 electrical characteristics these characteristics are guaranteed over the following conditions (unless otherwise stated): supply voltage, v dd = 5v 10%; ambient temperature, t amb = 0 c to 1 70 c (cg grade), 2 40 c to 1 85 c (ig grade). dc characteristics supply current, i dd , chip fully active cmos inputs with pullup resistors to v dd : rtcint, master/ slave, markfb (3:1), nanda, nandb, wprog, ale input voltage high input voltage low pullup resistor cmos inputs with pulldown resistors to v ss : mot/ intel, clksel, int in, tic in input voltage high input voltage low pulldown resistor cmos inputs without either pullup or pulldown resistors: masterreset, cs, wen, rw, masterclk (note 1), slaveclk, a (8:1), d (15:0), tck, tdi, tms, trst input voltage high input voltage low input leakage current ttl inputs with pullup resistors to v dd : sign (9:0), mag (9:0), plllockin, glonassbit input voltage high input voltage low pullup resistor ttl inputs with pulldown resistors to v ss : tscan, tcks, tdi1, tms1, tms2 input voltage high input voltage low pulldown resistor input for low level clocks: masterclk (note 1) peak to peak sinewave power level 1 outputs: tmag, tsign, tdo, tdo (7:1), nandop output voltage high output voltage low power level 3 outputs: 100/219khz, int out, sampclk, tic out, bite cntl, discop, timemark output voltage high output voltage low power level 1 outputs with tri-state: mag (9:2), sign (8:2), tck (7:1) output voltage high output voltage low output leakage current power level 3 output with tri-state: slaveclk output voltage high output voltage low output leakage current power level 6 output with tri-state: d (15:0) output voltage high output voltage low output leakage current bias output: bias units conditions max. typ. 08v dd 20 08v dd 20 08v dd 20 20 20 20 600 v dd 2 1 v dd 2 1 v dd 2 1 v dd 2 1 v dd 2 1 min. value characteristic 100 02v dd 250 02v dd 250 02v dd 10 08 250 08 250 04 04 04 10 04 10 04 10 v ss GP1020 5 address hold time ale pulse width ale valid to wen or rw valid (wprog = 1) ale valid to wen or rw valid (wprog = 0) address valid to ale low address valid to wen or rw valid cs high to ale valid cs low to wen or rw valid data hold time data setup time rw high to data at high impedance rw valid to data valid rw valid to wen high wen low to rw not valid write pulse width cs hold time after rw or wen not valid 25 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. timing characteristics (see figs. 4 to 9) conditions units characteristic value 10 20 5 20 20 20 10 0 10 30 10 10 15 15 30 0 min. symbol t ahold t alepw t alesetup t alvwrv t asetup t avwrv t chalv t cvwrv t dhold t dsetup t rhdz t rvdv t rwvwenh t wenlrwnv t wlwh t wrch note. this timing information is based on simulations and is not verified by measurement on each device. GP1020 bus timing diagrams wen cs ale a (8:1) d (15:0) rw (high) t alesetup t asetup t ahold address valid t alepw t cvwrv data valid t dsetup t dhold next r/w t wrhch t chalv t wlwh fig. 4 intel 486 mode write. mot/ intel = 0, wprog = 1 (write inhibited until ale falling edge) fig. 5 intel 486 mode read. mot/ intel = 0, wprog = 1 fig. 6 intel 186 mode write. mot/ intel = 0, wprog = 0 wen cs ale a (8:1) d (15:0) rw (high) t alvwrv t ahold address valid t avwrv t cvwrv data valid t dsetup t dhold next r/w t wrhch t chalv t wlwh fig. 7 intel 186 mode read. mot/ intel = 0, wprog = 0 rw cs ale a (8:1) d (15:0) wen (high) t alesetup t asetup t ahold address valid t alepw t cvwrv data valid t rvdv t rhdz next r/w t wrhch t chalv rw cs ale a (8:1) d (15:0) wen (high) t alvwrv t avwrv t ahold address valid t cvwrv data valid t rvdv t rhdz next r/w t wrhch t chalv
6 GP1020 GP1020 bus timing diagrams (continued) fig. 8 motorola 68xxx mode write. mot/ intel = 1, wprog = 0 fig. 9 motorola 68xxx mode read. mot/ intel = 1, wprog = 0 t alvwrv t avwrv t ahold address valid t cvwrv data valid t rvdv t rhdz next r/w t wrhch t chalv t rwvwenh wen cs ale a (8:1) d (15:0) rw t wenlrwnv signal processing overview each channel of the GP1020 is fed with a 2-bit (or optionally with a 1-bit) gps digital if at around 14mhz, from the input multiplexer that connects one of ten signal sources to the channel input. this signal is first brought to baseband using an on-chip digital mixer driven by a programmable digital local oscillator. it is then correlated with a c/a code internally gener- ated by a programmable gold code generator; the correlation result is the sum of the comparisons of individual code chips over a complete code period (an ?epoch? in gps terminology). a large positive or a large negative sum indicate good correlation but with opposite modulation, where the size of ?large? will depend on the current signal to noise ratio, while a small sum indicates poor correlation and the need to adjust the loops or choose another satellite. these results form the ?accumulated data? and are made available to the microprocessor to both control the tracking loops and to give the broadcast satellite data, the ?navigation mes- sage? when demodulated. periodically, the code epoch count, the code phase, and the carrier phase of all channels, are sampled at the same instant to form the ?measurement data? and are also made available to the processor. description of blocks (see fig. 10) clock generator the clock generator block generates the various clocks required in the GP1020, which can be operated either as a master or as a slave device. when it is operated as a master, the clock generator block is driven by a 40mhz clock provided by the accompanying front-end chip, the gp1010, and to drive the slaves a 20mhz output slave clk is provided. when the GP1020 is operated as a slave, it is driven only by this 20mhz slave clk from the master device. in the master the 40mhz is divided in a counter to form seven clock phases to control the data flow, but to get the same timing in the slaves twin 20mhz dividers use both high and low phases separately to give the effect of 40mhz clocking. when in master mode these seven phases are also used to generate a sampling clock (samp clk) output at 40mhz 4 7 = 571mhz, which drives the data sampling clock input of the gp1010. a 100/219khz output is provided for use as a micro- processor programmable interrupt clock. timebase generator the time base generator produces, among other signals: a 50505 m s free-running interrupt timebase int out, a free- running tic out signal with a period which may be selected to be either 100ms or 909ms (approximately), and a time mark signal with a 1 second period as an output which may be locked to gps time, utc, or the receiver timebase by programming its delay relative to the tic, based on recent navigation solutions. the tic is mainly used to latch measurement data (epoch count, code phase, code dco phase and integrated carrier phase ( = dco phase and cycle count)) of all six channels at the same instant. bite interface the bite interface block contains a register which allows control over the built-in-test functions of the chip. in addition, this register allows the processor to read the state of discrete input pins, such as plllockin connected to the status output of the gp1010, and also to set the state of the bite cntl and the discop output pins. these can in turn, for example, be used to drive the gp1010 bite input pin and the lna power on/off select, respectively. status registers the status registers block contains registers describing the status of accumulated and measurement data provided by each channel. signal selection block the signal selection block contains a multiplexer which can be programmed to direct any of the ten input sources to any of the six tracking channels. this is needed in glonass where frequency division multiplexing is used and separate local oscil- lators are needed to receive each satellite, leading to separate if filter channels. an input selector may be desirable in gps, which uses code division multiplexing, to allow the use of multiple antennae to overcome problems of incomplete sky visibility. for sign inputs, low = 2 , high = 1 ; for mag inputs, low = 1, high = 3. tracking module blocks the six tracking module blocks are all identical so that the term chx is used in the description to mean any of ch1, ch2, wen cs ale a (8:1) d (15:0) rw t alvwrv t ahold address valid t avwrv t cvwrv data valid t dsetup t dhold next r/w t wrhch t chalv t wlwh t rwvwenh t wenlrwnv
GP1020 7 master clk slave clk samp clk master/slave sign & mag tracking module channel 1 tracking module channel 2 tracking module channel 3 tracking module channel 4 tracking module channel 5 tracking module channel 6 2 tic input selector (dual 11 to 7 mux) timebase generator 2 10 sets of sign & mag input signals clocks ? ? ? clock generator tic in int in int out tic out timemark status register self test generator 8 7 8 7 7 7 7 7 bite interface self test generator statistics check microprocessor bus test sign & mag fig. 10 simplified overall block diagram ch3, ch4, ch5 or ch6 inputs or registers. they have the architecture shown in fig. 11. the individual sub-blocks are as follows: carrier dco the carrier dco is an accumulator performing additions at a constant rate and with a programmable increment value. it is used to synthesise the digital local oscillator signal required to bring the input signal to baseband in the mixer block, and must be adjusted away from nominal to allow for doppler shift and crystal frequency error. the nominal frequency of the output is 1405396825 mhz, set by loading the 26 bit chx_carr_incr register to 01f7b1b9 h and is programmed with a resolution of 4257475 millihertz. the very fine resolution is needed to keep the dco in phase with the satellite signal. code dco this block is a similar structure to the carrier dco block and is used to synthesise the oscillator signal required to drive the code generator at the proper chipping rate and phase. the nominal frequency of the output is 2046mhz, to give a chip rate of 1023mhz, and is set by loading the 25 bit chx_code_incr register to 016ea4a8 h and is programmed with a resolution of 8514949 millihertz. again,the very fine resolution is needed to keep the dco in phase with the satellite signal. code generator this generates the processor-selected gps gold code (one of prn code numbers 1 to 32 for normal satellites or 33 to 37 for ground based use) or the glonass code (fixed for all satellites) or one of eight inmarsat codes. twin generators are used to produce both a prompt (on-time) pattern and an early, late, or early-minus-late version for tracking use. at the end of each code sequence a signal dump is generated to latch the accumulated data, separately for each channel. mixer and correlator the mixer and correlator first mixes the digitised input signal with the carrier dco digital local oscillator to generate a signal at baseband, and then uses the code generator outputs to correlate the data stream. the block includes in-phase and phase-quadrature channels, as well as prompt and dithered (or early/late) correlator arms. the term dither is used in the GP1020 to mean a code channel in which the timing alternates one half-chip either before or after the prompt channel, and not the now obsolete technique of tau- dither, in which the prompt arm timing is oscillated a little each side of nominal to give tracking with only one arm. quadruple integrate and dump the bit-by-bit results from the correlator are passed to the quadruple integrate and dump block, which integrates the correlation result of individual code chips from all four correlators (in-phase and phase-quadrature, prompt and dithered arms) over a complete code period. through the accumulated data registers, the processor has access to each integration result. navigation or time reference receiver hardware system design a receiver system can use one or more GP1020s. when only one is used, that ic is operated in master mode, and when more than one are used, one of them is designated as being the master and all of the others are operated as slaves . in all cases, the master chip is the one which will receive the 40mhz master clk from the gp1010 and generate, upon release of the masterreset signal, a gated 20mhz clock which drives all slaves (if any) and allows a synchronised start-up. the master device also generates the samp clk signal which drives all of the gp1010 front-ends. the operating mode is programmed by tying the master/ slave pin to v dd for master or to v ss for slave operation. the operating mode sets the functions of master clk, slave clk and samp clk pins. the time mark signal is generated by the master GP1020; the slave time mark generator, although not disabled, is not synchronised with the master. the tic signal is generated by the master and routed to the slaves to ensure a common measure- ment data sampling instant for all the tracking channels. the slave tic out signal is not disabled but is not used. the master int out drives the slaves int in pins to provide latching of status bits at a common instant. optionally, the slave tic out and int out pins could be connected to the master tic in and int in pins, respectively, for testing purposes. when more than one GP1020 is used in the same system, the devices must share a common tic for sampling of measure- ment data to enable the software to calculate clock bias in the pseudoranges, and so find the correct ranges. each GP1020 contains a state machine driven by 7 different clock phases, so for two GP1020s to share a common tic, the devices must be synchronised. this is achieved by configuring the hard- ware as follows: ? all GP1020s share the same masterreset signal. ? one GP1020 is designated the master chip. it is
8 GP1020 1k bias 5k 10n 1-10n 600mv from gp1010 master clk GP1020 internal circuit fig. 12 biasing circuit for master clock input sign & mag 43mhz if sampled at57mhz to give 14mhz into GP1020 (via input selector) microprocessor bus 14-bit accumulate and dump clock tic code generator code dco epoch counters clock tic q_eol 14-bit accumulate and dump q_prompt eol c/a prompt c/a 14-bit accumulate and dump i_eol 14-bit accumulate and dump i_prompt 4 4 4 1 4 carrier cycle counter clock tic carrier dco clock tic 4 4 3 3 in-phase baseband quadrature baseband cos ( v t) 14mhz sin ( v t) 14mhz 2 fig. 11 tracking module simplified block diagram samp clk 40mhz 4 7 = 57142857mhz output when the chip is in master mode; nominal mark:space ratio is 1:1. this signal is held low during an active masterreset and when in slave mode. ticout output signal from tic generator, used to sample measure- ment data and so initiate a navigation solution. tic does not drive the microprocessor directly but sets a flag in meas_status_a , which should be be examined by reading the register periodically, such as at every int out. tic out is active high; active time duration is either 454545ms for a short tic or 90909ms for a long tic. the rising edge of tic out is in advance of the effective sampling instant inside the device by 125ns. the tic period is selectable via the tic_period bit of timer_cntl register to either 100ms minus 100ns (= 999999ms) or to 9.0909 ms. tic in the tic in input of a GP1020 is normally provided by a companion GP1020. its use is controlled by the tic_source bit of the timer_cntl register and is configured in most applications so the master tic out drives the slave tic in. programmed into this mode by tying the master/ slave pin to v dd (or by leaving it unconnected and relying on an internal pull-up resistor.) ? all other GP1020s are designated slaves and are programmed into this mode by tying their master/ slave pin to v ss . ? the master GP1020s samp clk output drives all of the gp1010 front-ends. this ensures that in a multiple gp1010 application, all of the signals are being sampled at the same instant in all gp1010s. the slave GP1020s have their sampling clk output left unconnected. ? the slave clk output from the master drives the slave clk inputs on all slaves. when the masterreset is released, the clock generators of all devices C master and slaves C are enabled. the slave clk output of the master device will start to toggle only after the masters clock generator has reached a certain phase (200ns after the masterreset release). the clock generator of the slave device gets reset into a state which corresponds to the next phase and starts counting as soon as the slave clk signal from the master reaches its slave clk input pin. important timing signals in a typical hardware design master clk the master clk is a 40mhz clock which sets the timing of all functions in a gps receiver using the GP1020. in a multiple GP1020 system only the master is given this clock and this may be connected in either of two ways, depending on the signal level. if the clock is a ttl signal it is directly connected to the master clk input and the bias output pin is left unconnected. the other option is an ac-coupled 600 mv peak-to-peak signal, when the bias output is used to set the dc voltage of the master clk pin as shown in fig. 12. the master clk pin on each slave GP1020 is not used and should be tied to v dd or v ss . slave clk 20mhz with 1:1 nominal mark:space ratio. output from master GP1020, input to slave, using a bidirectional buffer controlled by master/ slave. this signal is held low when the master chip is reset and starts to toggle within 200ns after masterreset is released.
GP1020 9 (e.g. arinc 743 may be wanted) or a simple reference time clock may be built. to synchronise time mark to gps time the first stage is to acquire the measurement data at any arbitrary tic and then calculate the full navigation solution to give the time at that tic. from this determine a later tic at which to acquire data again such that after the navigation solution computation delay (typi- cally a few tic periods long) a further delay may be programmed into down_count_hi and _lo registers to start on the next tic, to give time mark at the required gps whole second. this is rather a long process to get started, but once the first correct tic choice and down counter delay are known the process can roll on with each tic and delay calculation coming from the previous navigation solution. to get utc instead of gps time it is only neccessary to read the navigation message to get the number of whole seconds difference and add this to the calculated gps time. a possible refinement is to calculate the oscillator drift over several meas- urements and use this to extrapolate a better value for the delay counter. the ultimate accuracy that can be achieved is very good, but to get this the crystal must both have high stability and be drift compensated in the software; in addition, the receiver front-end delay must be known and allowed for, and the delay through the output drivers and cables must be allowed for by using the markfbx pins. if, as is likely, selective availability is on it will be the main source of error in a well designed time mark system, but better than one microsecond absolute accuracy is still possible. to reduce the effects of sa it is possible to use a stable rubidium reference oscillator and average the induced offsets over a long time to give very good peak errors of a few tens of nanoseconds. as the main purpose of the time mark output is a timing reference signal at one pulse per second for the electronic systems in an airliner, it must be both accurate and known to be accurate. the accuracy is achieved by loading down_count_hi and _lo with the correct offset in 50ns units from the gps measuring tic. as the tic rate is nominally 1ppm less than 10hz, the down_count value should be expected to in- crease at around 1 m s per one second time mark, a number change of 1 20 each pulse. this value will need continuous fine tuning to allow for the stable and variable crystal errors. integrity is ensured in two ways; first, by using prop_delay to check the delay through line drivers and to verify that a time mark really did occur and, secondly, by having a complex handshake sequence so that any failure in the hardware will be detected by the microprocessor. the handshake sequence is: 1. write to down_count_lo to arm the time mark gen- erator (this requires that down_count_hi is already written; as it rarely changes,this is often automatically true). 2 . at next tic the GP1020 will start down_count. 3. the GP1020 will give a time mark pulse output and start the prop_delay counter. 4. feed time mark back through mark_fbx input to stop prop_delay and to set mark_fb_ack in meas_status_a 5. read meas_status_a, normally as part of the measure- ment data transfer protocol but, on this occasion, to also clear the overwrite protection on prop_delay and to clear the mark_fb_ack bit. 6. read prop_delay, once mark_fb_ack has been set (and cleared) to give a stable value for the last delay. this also re-enables the time mark generator ready for a repeat of step (1) to take effect. this may seem rather complicated, but is only needed once per second and so is little overhead if a simple system is all that is required. for a full accuracy system, the various register operations fit in with the computations needed to achieve full arinc 743 specification. int out this output signal is a free running interrupt timebase which may be used to interrupt the microprocessor to initiate data transfer sufficiently often that no correlation results will be missed. the tracking loops rely on the microprocessor to adjust the dco registers in response to signal changes so the rate of interaction must be sufficiently high. if the frequency of int outis too high for the software to process then a polling scheme may be used, by inhibiting the interrupts (int_mask bit in timer_cntl set low) and then periodically writing to status_latch and reading the status registers to check if new data is available. the period of int out is programmable; a typical value is 50505 m s. during masterreset the interrupt output is stopped and the pin is held low if in intel mode, or high if in motorola mode. the active duration of int out (high for intel, low for motorola) is 252525 m s, which should be more than adequate to ensure that the interrupt controller in the processor will have time to respond. int in this input signal is normally provided by the int out output of a companion GP1020; in general the master drives the slave. it is used, when selected via the int_source bit of the timer_cntl register, to latch the state of the status bits. 100khz/219khz a clock output at either 100khz or 219khz which may be used to drive the microprocessor interrupt timer. the frequency is set by the level on clksel (high for 100khz and low for 219khz). masterreset when masterreset is set low , all the registers, accu- mulators and counters are cleared, except chx_cntl, which is initialised to specific values (refer to detailed description of the registers for these values). when the device is held reset, by masterreset set low, the following pins are driven as listed: master clk: this input may or may not be being exter- nally driven during the reset. masterreset internally gates master clk to ensure a well defined level on all clock lines until the release of masterreset; the release of masterreset must occur only when the input buffer is properly biased and the input signal is stable. slave clk: configured as an input on slave devices and held low on master device. samp clk: held low. 100 / 219khz: this output is held low when master reset is active (also low) and toggles to high shortly after masterreset is released, and then runs normally. d0-d15: high impedance. bite cntl: low. disc op: low. tic out: low. int out: this output is held low until interrupt inhibit is removed, when in intel bus type mode, or is held high until the inhibit is re- moved, when in motorola bus type mode. time mark the primary purpose of the time mark output is to give a one pulse per second signal locked to utc or gps time. this may be followed by the correct time from the microprocessor and could be used as a reference by other navigation instruments
10 GP1020 bit setting 7654 3210 0001 0101 0010 0110 0011 0111 0100 1xx0 0000 1xx0 0001 1xx1 0000 0111 0001 1xx0 0010 1xx1 0001 0010 0010 0011 0100 0101 0101 0110 0110 0111 0111 1xx0 1xx0 1xx1 0000 0011 0001 0100 0010 0101 0011 0110 0100 0111 0101 1xx0 0000 0010 0011 0101 0100 0110 0101 0111 0110 1xx0 0111 1xx1 0000 0101 0001 0110 0010 0111 0011 1xx0 0100 1xx1 0011 1xx1 0000 0110 0001 0111 0011 1xx1 gps prn reference number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33* 34* = 37 35* 36* 37* = 34 selected taps to be exored together 2 3 4 5 1 2 1 2 3 2 3 5 6 7 8 9 1 2 3 4 5 6 1 4 5 6 7 8 1 2 3 4 5 4 1 2 4 6 7 8 9 9 10 8 9 10 3 4 6 7 8 9 10 4 5 6 7 8 9 3 6 7 8 9 10 6 7 8 9 10 10 7 8 10 satellite code selection this section describes the code selection for normal gps and glonass operation; for inmarsat codes and unusual tech- niques see full details in detailed description of regis- ters section, under chx_cntl. the same section gives details of the other bits of chx_cntl. the satellite code to be used by each channel is set by the chx_cntl registers, which are addressed individually from the a8-a1 address bus by: 00 h : read/write to channel 1 10 h : read/write to channel 2 20 h : read/write to channel 3 30 h : read/write to channel 4 40 h : read/write to channel 5 50 h : read/write to channel 6 70 h : write only, to all channels simultaneously the one glonass code may be selected by setting bit 10 high, otherwise this bit should be set low and bits 7 to 0 used to select one of the gps gold codes (see table opposite). software requirements the very wide variety of types of gps or glonass receiver need to operate the correlator in different ways so, to accomodate this and also to allow dynamic adjustment of loop parameters, the GP1020 has been designed to use software for as many functions as possible. this flexibility means that the device cannot be used without a microprocessor closely linked to it, but as a processor is always needed to convert the output of the GP1020 into useful information this is not a significant limitation. the software associated with the GP1020 can be divided into two separate modules: one to acquire and track satellite signals to give pseudoranges and another to process these to give the navigation solution and format it in a form suitable for the user. for the navigation solution to be possible all of the pseudoranges must have exactly the same clock error, which can then be removed iteratively to give real ranges if sufficient satellites are tracked (3 if the height is known, otherwise 4). this need for exact matching of timing errors explains the need for all of the compli- cated synchronisation between all channels and between mas- ter and slaves. the following relates only to the signal processing aspects of the software, to acquire and track signals from up to six satellites per GP1020 and to obtain the pseudoranges and the navigation message. the operation of the navigation software is not dependent on the details of the correlator, and so does not need to be included in this data sheet. an on-chip interrupt time base int out is provided to help implement a data transfer protocol between the microprocessor and the GP1020 at fixed time intervals, otherwise a software based polling scheme will be needed e the choice is set by the application. if int out is used, and perhaps also if polling is used, the data transfer rate is about twice the correlation result rate for each channel, so many transfers will not give new data. bus use can be reduced by examining the status registers before each transfer to see if new data is available and then only reading the data if it useful. it is important to note that the timing of each of the correlator channels will be locked to its own incoming signal and not to each other or to the microprocessor interrupts, so new data is gener- ated asynchronously. the sampling instant of measurement data of all channels, however, is common to give a consistent navigation solution. in order to acquire lock to the satellites as quickly as possible, the data from the last fix should be stored as a starting point for the next fix. it is also useful to have a real-time clock built into the receiver to give a good estimate of gps time for the next fix; the navigation solution can be used to measure clock drift and calculate a correction for the clock to overcome ageing. the user?s location (or a good estimate of it) along with the almanac and the correct time will indicate which satellites should be searched for and may be used to find an estimate of doppler effects, while the previous clock error is the best available estimate of the present clock error. if this information is not available then the receiver must scan a much wider range of values, which will greatly increase the time to lock. the satellite clock correction and ephemeris are needed for the navigation solution, so if a recent set is held in memory the calculations may begin as soon as lock is achieved and not need to wait for the re- transmission (18 to 36 seconds). this description applies to just one tracking channel but is the samd this is not necessarily the same as the other channels. the GP1020 contains four different types of registers: control registers which are used to program functions of the device. status registers which provide a status indication of the process taking place in the device. accumulated data registers which provide the results of correlation with the c/a code every millisecond. this is the raw data used to acquire and track satellite signals. measurement data registers which latch the carrier dco phase, carrier cycle count, code dco phase, 1 millisecond gps gold codes. *note that these codes, 33 to 37, are reserved for non-satellite use only.
GP1020 11 epoch, and the 20 millisecond epoch count at every 9.09 or 100 milliseconds interval. this is the raw data used to compute pseudorange. software sequence for acquisition satellite signals seen by a gps receiver are so weak that they are buried in the noise and can only be detected by correlation. the spectrum of each signal is spread, using 1023 chip gold codes for gps or a 511 chip maximal length code for glonass; to correlate them therefore, a locally generated code must be chosen to precisely match the spreading code type, rate, and phase. this pattern is then multiplied bit-by-bit with the incoming data stream and the results integrated over the code length to recover the signal. the process of signal acquisition is simply the matching of receiver settings to the actual signal values. to make matters more complicated the satellite carrier frequency is shifted a little by the doppler effect due to the motion of the satellite, the user clock will drift randomly, and (in most situations) the signal to noise ratio is poor for some satellites. as a result, the software must be ?wide-band? to find the signal and also ?narrow-band? to reduce noise, leading to very different programs in different applications. for all tracking channels, the signal processing software needs the following sequence of activities: 1. program chx_cntl register to select the desired gps gold code (prn number) for the selected satellite and code type for the mode of the correlator dithering arm e it is often best, when in acquistion mode, to fix the dithering arm at early or at late and do a search in two phases at once and then switch to a tracking mode once a satellite is found. 2. program chx_carr_incr_lo and chx_carr_incr_hi the values programmed into these two registers are concatenated and set the local oscillator frequency for the digital mixing performed in the GP1020 to bring the incoming 2-bit digitised signal down to baseband. the value to be programmed is equal to the nominal local oscillator frequency plus the estimated doppler shift compensation plus the estimated user clock frequency drift compensation. 3. program chx_code_incr_lo and chx_code_incr_hi the value to be programmed in these registers represents twice the nominal chipping rate of the c/a code (2.046 mhz) plus, if desired, a small compensation for the doppler shift and for the user clock frequency drift. 4. release the tracking channel reset by programming the reset_cntl register with the proper value. this will cause the correlation process to start. 5. obtain accumulated data from accumulated data register readings. several consecutive readings on the same tracking channel can be added to increase, at will, the integration period of the correlation. 6. decide if the gps signal has been found by comparing the correlation result with a threshold. if found then jump to a signal pull-in algorithm. note that both in-phase and phase quadrature accumulated data have to be considered since at this time, the carrier dco local oscillator phase is not necessarily in phase with the incoming gps signal. 7. if the gps signal has not been found, a new trial has to be made with different carrier dco, code dco, or gold code phase programmings. typically, both dcos would be held constant while the gold code phase is varied to try all of the 2046 half chip positions possible, then the carrier dco would be programmed with slightly different values and the gold code phase positions would again be scanned. the gold code phase is varied by programming the chx_code_slew register and can be varied by increments of half a code chip. 8. once the gps signal has been found, the code phase alignment, the carrier phase alignment and the doppler and user clock bias compensations are still coarse. the code phase alignment is only within a half code chip, the carrier dco is not in phase with the incoming signal and its frequency is still in error by up to the increment used for successive trials. the signal processing software must next use a pull-in algorithm to refine these alignments. there are many suitable types of algorithm to choose from, such as successive small steps until the error is too small to matter, like an analog pll, or by using more complicated signal processing to estimate the errors and jump to a much better set of values. the signal pull- in algorithm will then program chx_carr_incr_lo/hi regis- ters with more accurate values for the carrier dco. corrections to the gold code phase smaller than a half chip cannot be done by programming chx_code_slew registers in the code generator, but should set chx_code_incr_lo/hi registers to steer the code dco and gradually bring the gold code phase to the right value. signal tracking the incoming gps signal will exhibit a doppler shift which varies with time due to the non-uniform motion of the satellite relative to the receiver, and the user clock bias is likely to also vary with time. the net result is that unless dynamic corrections are applied to the code and carrier dcos, the gps signal will be lost. this leads to two servo loops being required: one to maintain lock on the gold code phase and a second to maintain lock on the carrier. with the GP1020 these servo loops are implemented in the signal processing software. the raw data used to steer the two servo loops is the accumulated data, which is output by the tracking channel at the rate of once per millisecond. the dithering arm accumulated data is used for the gold code loop; some approaches use an ?early minus late? gold code to implement a null steering loop, others use a dithering code which alternates between a code one half chip late and a code one half chip early. in the GP1020, the dithering rate is 20 ms (20 code epochs) each way, starting with early after a reset, when this type of code is selected through the chx_cntl register. the gold code loop is closed by regularly updating the code dco frequency using the chx_code_incr_lo/hi registers. the prompt arm accumulated data is used for the carrier phase loop (although the dithering arm may also be used). one approach consists of varying the carrier dco phase in order to maintain all the correlation energy in the in-phase correlator arm and none in the phase quadrature correlator arm. the carrier phase loop is closed by regularly updating the carrier dco frequency using the chx_carr_incr_lo/hi registers. data demodulation the c/a code is modulated with space vehicle (sv) data at 50 baud to give the navigation message. this modulation is an exclusive-or function of the c/a code with the sv data. this means that every 20 milliseconds (which is every 20 c/a code epochs), the c/a code phase will be reversed (shifted by 180 degrees) if the new data bit is different from the previous one. on the prompt arm, once the signal is being correctly tracked, such a data bit transition will change the sign of the accumulated data. data demodulation can then be achieved in two stages: 1. locate the instants of data bit transitions to identify which c/a code epoch corresponds to the beginning of a new data bit. this will allow initialisation of the GP1020 epoch counters by the signal processing software (through the chx_1ms_ and 20mse epoch registers) to count code epochs from 0 to 19 in phase with data bits. at each new cycle of the 1 ms epoch counter, the 20 ms epoch counter will increment.
12 GP1020 2. record the sign of accumulated data on the prompt arm for each data bit period of 20 ms, with filtering to reduce the effect of noise on the signal. note that there is a sign ambiguity in the demodulation process in that it is not possible to tell which data bits are ?0?s and which are ?1?s from the signal itself. this ambiguity will be resolved at a later stage when the full naviga- tion message is interpreted. pseudorange measurement the measurement data registers provide the raw data neces- sary to compute the pseudorange. this raw data is a sample, at a given instant set by the GP1020 tic, of the 20 ms and 1 ms epoch counters, the c/a code phase counter and the code dco phase. by definition, the pseudorange is expressed in time units and is equal to the satellite-to-receiver propagation delay plus the user clock bias. the user clock bias is first estimated (blind guessed is more likely with a cold start, but iteration then takes longer) and then obtained as a by-product of the navigation solution. the pseudorange is equal to the user?s apparent local time of reception of the signal (t 1 ) minus the gps real time of transmission (t 2 ). with the demodulated data, the software has access to the space vehicle navigation message, which contains information on the gps system time for the transmission of the current subframe; this is equal to term t 2 . the time information in the navigation message allows the receiver time to be initialised with a resolution of 20 milliseconds (one data bit period) but with knowledge of the precision to much better than one c/a code chip e a little less than 1 microsecond. as the time- of-flight from the satellite to the receiver is in the region of 60 to 80 milliseconds an improved first guess for local time could include an allowance for this delay to reduce the iteration time later. by using the data to time-tag the tic, along with the values of the epoch counter, the code generator phase, and the code clock phase it is possible to measure the time of the sv signal in local apparent time. this gives the value of t 1 needed for the pseudorange measurement. the pseudorange can now be computed as t 1 2 t 2 . the error present in the time setting is the initial value of the user clock bias, with an allowance for the various counter phases. once a navigation solution has been found the clock error is precisely known and may be used for future pseudorange calculations. because the receiver clock drifts with time, the clock bias changes with time and must be tracked by the navigation software.
GP1020 13 GP1020 register addresses and content overall memory map the GP1020 internal registers are addressed using 8 address lines, a1 to a8. this section gives an overview of the register names with their addresses. a detailed memory map is shown in the table of registers. address range register block accessed (hex) 00 to 07 access to control registers of tracking channel 1 10 to 17 access to control registers of tracking channel 2 20 to 27 access to control registers of tracking channel 3 30 to 37 access to control registers of tracking channel 4 40 to 47 access to control registers of tracking channel 5 50 to 57 access to control registers of tracking channel 6 70 to 77 for write operations only. access to all identical control registers of all tracking channels with one single operation. the same data gets written in these registers. 80 to 83 access to accumulated data and measurement data status 84 to 9b access to in phase and quad phase accumulated data registers and sbr (status bit reset) commands of all tracking channels. 9c,9d access to all identical sbr (status bit reset) commands of all tracking channels with a single write operation. a0 to b7 access to measurement data registers of all tracking channels. bc to bf for write operations only. access to all identical measurement data registers of all tracking channels with one single operation. the same data gets written in these registers. c0 to c8 access to bite interface, time_base_gen, reset_cntl, signal selector and test registers. other addresses not used. do not access these addresses. note 1: registers are not all read/write. to minimise the hardware, some addresses are shared between read-only and write-only registers having different functions. refer to table of registers for more details. table of registers address register (hex) read function write function 00 ch1_cntl ch1_cntl 01 ch1_tst_code_slew ch1_sig_sel 02 ch1_epoch_chk ch1_code_incr_hi 03 ch1_shift_reg ch1_code_incr_lo 04 not used ch1_carr_incr_hi 05 not used ch1_carr_incr_lo 06 not used ch1_tst_code_phase 07 not used ch1_tst_cycle 08 not used not used 09 not used not used 0a not used not used 0b not used not used 0c not used not used 0d not used not used 0e not used not used 0f not used not used 10 ch2_cntl ch2_cntl 11 ch2_tst_code_slew ch2_sig_sel continued...
14 GP1020 table of registers (continued) address register (hex) read function write function 12 ch2_epoch_chk ch2_code_incr_hi 13 ch2_shift_reg ch2_code_incr_lo 14 not used ch2_carr_incr_hi 15 not used ch2_carr_incr_lo 16 not used ch2_tst_code_phase 17 not used ch2_tst_cycle 18 not used not used 19 not used not used 1a not used not used 1b not used not used 1c not used not used 1d not used not used 1e not used not used 1f not used not used 20 ch3_cntl ch3_cntl 21 ch3_tst_code_slew ch3_sig_sel 22 ch3_epoch_chk ch3_code_incr_hi 23 ch3_shift_reg ch3_code_incr_lo 24 not used ch3_carr_incr_hi 25 not used ch3_carr_incr_lo 26 not used ch3_tst_code_phase 27 not used ch3_tst_cycle 28 not used not used 29 not used not used 2a not used not used 2b not used not used 2c not used not used 2d not used not used 2e not used not used 2f not used not used 30 ch4_cntl ch4_cntl 31 ch4_tst_code_slew ch4_sig_sel 32 ch4_epoch_chk ch4_code_incr_hi 33 ch4_shift_reg ch4_code_incr_lo 34 not used ch4_carr_incr_hi 35 not used ch4_carr_incr_lo 36 not used ch4_tst_code_phase 37 not used ch4_tst_cycle 38 not used not used 39 not used not used 3a not used not used 3b not used not used 3c not used not used 3d not used not used 3e not used not used 3f not used not used 40 ch5_cntl ch5_cntl 41 ch5_tst_code_slew ch5_sig_sel 42 ch5_epoch_chk ch5_code_incr_hi 43 ch5_shift_reg ch5_code_incr_lo 44 not used ch5_carr_incr_hi 45 not used ch5_carr_incr_lo 46 not used ch5_tst_code_phase 47 not used ch5_tst_cycle 48 not used not used 49 not used not used 4a not used not used 4b not used not used 4c not used not used 4d not used not used 4e not used not used 4f not used not used continued...
GP1020 15 table of registers (continued) address register (hex) read function write function 50 ch6_cntl ch6_cntl 51 ch6_tst_code_slew ch6_sig_sel 52 ch6_epoch_chk ch6_code_incr_hi 53 ch6_shift_reg ch6_code_incr_lo 54 not used ch6_carr_incr_hi 55 not used ch6_carr_incr_lo and add_dat_tst 56 not used ch6_tst_code_phase 57 not used ch6_tst_cycle 58 not used not used 59 not used not used 5a not used not used 5b not used not used 5c not used not used 5d not used not used 5e not used not used 5f not used not used 60 to 6f not used not used 70 not used all_cntl 71 not used all_sig_sel 72 not used all_code_incr_hi 73 not used all_code_incr_lo 74 not used all_carr_incr_hi 75 not used all_carr_incr_lo 76 not used all_tst_code_phase 77 not used all_tst_cycle 78 not used not used 79 not used not used 7a not used not used 7b not used not used 7c not used not used 7d not used not used 7e not used not used 7f not used not used 80 meas_status_a status latch 81 meas_status_b not used 82 accum_status_a not used 83 accum_status_b not used 84 ch1_i_dith ch1_meas_rst 85 ch1_q_dith ch1_accum_rst 86 ch1_i_prompt not used 87 ch1_q_prompt not used 88 ch2_i_dith ch2_meas_rst 89 ch2_q_dith ch2_accum_rst 8a ch2_i_prompt not used 8b ch2_q_prompt not used 8c ch3_i_dith ch3_meas_rst 8d ch3_q_dith ch3_accum_rst 8e ch3_i_prompt not used 8f ch3_q_prompt not used 90 ch4_i_dith ch4_meas_rst 91 ch4_q_dith ch4_accum_rst 92 ch4_i_prompt not used 93 ch4_q_prompt not used 94 ch5_i_dith ch5_meas_rst 95 ch5_q_dith ch5_accum_rst 96 ch5_i_prompt not used 97 ch5_q_prompt not used 98 ch6_i_dith ch6_meas_rst 99 ch6_q_dith ch6_accum_rst continued...
16 GP1020 table of registers (continued) address register (hex) read function write function 9a ch6_i_prompt not used 9b ch6_q_prompt not used 9c not used all_meas_rst 9d not used all_accum_rst 9e not used not used 9f not used not used a0 ch1_epoch_a ch1_1ms_epoch a1 ch1_epoch_b ch1_preset_phase a2 ch1_carr_dco_phase ch1_code_slew a3 ch1_carr cycle ch1_20ms_epoch a4 ch2_epoch_a ch2_1ms_epoch a5 ch2_epoch_b ch2_preset_phase a6 ch2_carr_dco_phase ch2_code_slew a7 ch2_carr cycle ch2_20ms_epoch a8 ch3_epoch_a ch3_1ms_epoch a9 ch3_epoch_b ch3_preset_phase aa ch3_carr_dco_phase ch3_code_slew and add_dat_tst ab ch3_carr cycle ch3_20ms_epoch ac ch4_epoch_a ch4_1ms_epoch ad ch4_epoch_b ch4_preset_phase ae ch4_carr_dco_phase ch4_code_slew af ch4_carr cycle ch4_20ms_epoch b0 ch5_epoch_a ch5_1ms_epoch b1 ch5_epoch_b ch5_preset_phase b2 ch5_carr_dco_phase ch5_code_slew b3 ch5_carr cycle ch5_20ms_epoch b4 ch6_epoch_a ch6_1ms_epoch b5 ch6_epoch_b ch6_preset_phase b6 ch6_carr_dco_phase ch6_code_slew b7 ch6_carr cycle ch6_20ms_epoch b8 not used not used b9 not used not used ba not used not used bb not used not used bc not used all_1ms_epoch bd not used all_preset_phase be not used all_code_slew bf not used all_20ms_epoch c0 reset_cntl reset_cntl c1 bite bite c2 rtc_delay timer_cntl c3 prop_delay_lo down_count_hi c4 prop_delay_hi down_count_lo c5 stat_chk_sign stat_chk_sel c6 stat_chk_mag not used c7 add_dat_tst add_dat_tst c8 not used tdata_duty_cycle c9 to ff not used not used
GP1020 17 detailed description of registers the registers are listed in alphabetical order and not in address order to allow easy reference to each section. accum_status_a read address 82 h register bit mapping bit bit name lsb 0 ch1_new_accum_data 1 ch2_new_accum_data 2 ch3_new_accum_data 3 ch4_new_accum_data 4 ch5_new_accum_data 5 ch6_new_accum_data 6 not used 7 not used 8 ch1_early_lateb 9 ch2_early_lateb 10 ch3_early_lateb 11 ch4_early_lateb 12 ch5_early_lateb 13 ch6_early_lateb 14 not used msb 15 new stat_data register operation accum_status_a is a latch register containing the state of status bits prevailing at time of sampling. the status bits are sampled and latched on the positive edge of every int out or int in signal. they can also be sampled and latched on request by performing a write operation to status_latch (location 80 h ). latching the status bits ensures glitch-free reading of accum_status_a. bit description the following bits are all active high: chx_new_accum_data status bit indicates if there is new accumulated data available to be read. each indi- vidual bit can be cleared with a write operation at chx_accum_reset location or by disabling the propa- gation of clocks (chx_rstb bits of reset_cntl). this also releases the overwrite protection. each bit is also cleared on the trailing edge of a read of the associated q_prompt register. if new accumulated data becomes available after accum_status_a bits have been latched, the overwrite protection is not cleared while reading the q_prompt register and the chx_new_accum_data bit will be set at the next latching of accum_status_a. chx_early_lateb status bit indicates whether the accumulated data on the dithering arm of the tracking channel results from correlation with early or late code. a high indicates an early code and a low indicates a late code. each individual bit is updated at each dump when the overwrite protection is not active. when the early-minus-late code is selected for a particular channel, this status bit has no meaning. new_stat_data status bit when high indicates that new statistical data is available in the stat_chk_sign and stat_chk_mag registers. it is cleared when a stat_chk_mag read operation is performed if a valid state had been latched previously or by a write operation at all_accum_reset location. the first statistical data after a power up is not representative and should be cleared. all status bits are reset by a hardware or software master reset. accum_status_b read address 83 h register bit mapping bit bit name lsb 0 ch1_missed_accum 1 ch2_missed_accum 2 ch3_missed_accum 3 ch4_missed_accum 4 ch5_missed_accum 5 ch6_missed_accum 6 not used 7 not used 8 ch1_ovfl_accum 9 ch2_ovfl_accum 10 ch3_ovfl_accum 11 ch4_ovfl_accum 12 ch5_ovfl_accum 13 ch6_ovfl_accum 14 not used msb 15 not used register operation accum_status_b bits are sampled and latched on the positive edge of every int out or int in signal. they can also be sampled and latched on request by performing a write operation to status_latch (location 80 h ). bit description chx missed_accum status bit indicates if there has been missed accumulated data. when active high, this status bit is latched until (i) a master reset (hardware or software) or (ii) a write operation to chx_accum_reset with don?t care data or (iii) the propagation of clocks is disabled (chx_rstb bits of reset_cntl). chx_ovfl_accum status bit indicates if there has been an overflow in any of the channel accumulated data registers. this bit is active high and is updated at each dump when the overwrite protection is not active. it gets reset whenever the associated chx_accum_reset is written into with don?t care data or upon a master reset (hardware or software) or by disabling the propagation of clocks (chx_rstb bits of reset_cntl). add_dat_tst read/write address c7 h this register is used to test the address bus and data bus hardware connections to the inputs of the chip. it allows the system to verify that there is no short between pins or input lines in the chip or on the board. register bit mapping bit description 15 to 8 contents of address bus or most significant bits of data bus. 7 to 0 contents of least significant bits of data bus. register operation this register is a read/write register. upon a master reset (software or hardware) the register is cleared. when a write is performed at address aa h or 55 h the most significant bits of the register will be loaded with the address bus value present on the bus, aa h or 55 h if the address bus is working properly and the least significant bits of the register will keep their previous value.
18 GP1020 when a write is performed at address c7 h the register will be loaded with the data bus value present on the bus. when a read operation is performed to c7 h it reads all the bits previously loaded. it is recommended that the test is performed as follows in order to verify that the address and data bus operate properly. address bus test: write to address 55 h (the data bits are don?t care) read the most significant bits at address c7 h (the 8 least significant bits are 00 h if no access had been done to the address c7 h ). if the value is not 5500 h a problem is detected on the address bus. write to address aa h (the data bits are don?t care) read the most significant bits at address c7 h . if the value is not aa00 h a problem is detected on the address bus. note : when writing to addresses 55 h and aa h , the ch6_carr_incr_lo and ch3_code_slew registers will also be written into with the values on the data bus. data bus test: write 5555 h to address c7 h read the register at address c7 h . if the value is not 5555 h a problem is detected on the data bus. write aaaa h to address c7 h read the register at address c7 h . if the value is not aaaa h a problem is detected on the data bus. bite read/write address c1 h register bit mapping bit description 0 bitecntl 1 discop 2 pll_locka (state) 3 pll_lockb (negative transition) 4 glonass bit 5 self_test_en 6 self_test_source 7 meander 8 carr_mix_enb bit description bitecntl bit: drives the bite input of the gp1010. set inactive low by a master reset. when high, the gp1010?s pll is unlocked and the 40 mhz signal be- comes unstable. the GP1020 should be put into hardware master reset mode for the time needed to allow the gp1010?s 40 mhz output to stabilise. disc o/p: discrete output with no specific function. low at power up and its state will follow the value written in the bite register. pll_locka: input from gp1010, read only, to indicate the state of the pll lock signal; a high indicates a locked condition. this discrete input can be used for other purposes. pll_lockb: input from gp1010, indicates that a nega- tive transition of the pll lock signal (from locked to unlocked state) has been detected and latched in the GP1020. a high indicates a negative transition. this bit is cleared by the trailing edge of a read to bite register operation. glonass bit: test input from glonass front end. a high on this pin sets register bit high. this discrete input can also be used for other purposes. self_test_en: active high. when inactive (low) the self-test signal generator is disabled and tsign and tmag output pins are held low. when active the self-test signal generator is enabled and tsign and tmag output pins are toggling. the injection back into the input of the tracking channels is controlled by chx_signal_sel. self_test_source: when low, the tracking chan- nel 1 is used as a signal source for the self-test signal generator. when high, the tracking channel 2 is used as a signal source for the self-test signal generator. meander: when high, the self-test generator will modulate the data bit stream with a meander. this is required when glonass operation has to be tested. carr_mix_enb: when low, all carrier mixers operate normally. when high, all carrier mixers are disabled and the incoming sign and magnitude data passes through without being affected. chx_accum_reset write addresses 85, 89, 8d, 91, 95, 99 h and all_accum_reset write address 9d h these are write-only locations provided to allow resetting of all the status bits associated with a given channel in accum_status_a and accum_status_b. all_accum_reset access will also clear the new_stat_data flag in accum_status_b register. when these locations are written into, the data is don?t care. but if the cnttestmode bit (chx_20ms_epoch register) is active, g1 and g2 registers will be set at the 1023rd chip of the code sequence. this operation accelerates the test process by gen- erating accumulated data and status bits when the code steps to the first chip and so generating a dump in the associated channel. chx_carr_cycle read addresses a3, a7, ab, af, b3, and b7 h this register contains the 16 more significant bits of a variable containing the number of carrier dco cycles that occurred during the last tic period ending at a tic. the value is sampled and latched on the tic. while reading measurement data associated with a given channel, chx_carr_cycle must be read last because the trailing edge of a read to this register will release the overwrite protection mechanism of measurement data for this channel. carr_cycle: principle of operation in the chx_carr_cycle register and counter a tic gen- erates two consecutive actions: 1. it latches the 16 more significant bits of the cycle up counter into carr_cycle and the 2 less significant bits into carr_dco_phase. 2. it resets the cycle up counter. after each tic, every time the carrier dco accummulator generates an overflow as a result of a carrier cycle being completed, the cycle up counter counts up by one. the number of bits needed for the counter was established as follows: for gps, the nominal carrier dco frequency with no doppler and no oscillator drift compensation is 1405396825 mhz, so in 100 ms, there will be about 140,540 cycles. for glonass signals, the carrier dco frequency wil vary depend- ing on the particular satellite being tuned, between 1429 - 06 mhz and 1429 + 06 mhz, a maximum of 2029 mhz, giving 202,900 cycles in 100 ms. the maximum number of cycles, carr_count max, will also depend on the maximum doppler and oscillator drift com- pensation to be allowed for, hence the counter must be able to count to a number greater than 140,540 or 202,900. the highest frequency required is then 2029 mhz plus a few
GP1020 19 tens of kilohertz to allow for oscillator drift and doppler compen- sation. an 18 bit counter will cover up to 262,143 cycles, which is more than adequate. register contents range chx_carr_cycle is a 16 bit register, unsigned, and the validity range of the data is 0 to 2 16 2 1. chx_carr_cycle content is protected by the overwrite protection mechanism of measurement data. thus for an overwrite to occur, either the associated chx_new_meas_data status bit has to be cleared or chx_carr_cycle itself has to be read. chx_carr_dco_phase read addresses a2, a6, aa, ae, b2, b6 register bit mapping bit description 9 to 0 most significant bits of chx_carr_dco phase accumulator. the weight of the least significant bit is 2 p /1024 radian. these bits form an unsigned integer valid from 0 to 1023. chx_carr_dco_phase provides the sub-cycle integrated phase measurement information and therefore complements the information given by chx_carr_cycle 11 and 10 least significant bits of the number of carrier dco cycles that occurred during the last tic period ending at a tic. the value is sampled and latched on the tic. 15 to 12 not used. the register value is latched on a tic and protected from overwrite by the overwrite protection mechanism of measure- ment data. accumulator overflow 2 carrier dco accumulator clk en cycle up counter reset data load carr_cycle register latch 16 enable data bus carr_dco_phase register latch tic fig. 13 chx_carr_cycle block diagram chx_carr_incr_hi & chx_carr_incr_lo and all_carr_incr_hi & all_carr_incr_lo write addresses 04 & 05, 14 & 15, 24 & 25, 34 & 35, 44 & 45, 54 & 55 and 74 & 75 h register bit mapping bit description carr_incr_hi 9 to 0 more significant bits of the carrier dco phase increment. carr_incr_lo 15 to 0 less significant bits of the carrier dco phase increment. register operation the registers carr_incr_lo and carr_incr_hi are combined to form the 26 bits of the carr_incr register, the carrier dco phase increment. both registers are write-only registers and can be written to at any time. the first write must be performed on carr_incr_hi and the second write on carr_incr_lo. the written value is latched in the carr_incr register on the trailing edge of a write to carr_incr_lo. it is possible to perform a write only to carr_incr_lo register if the carr_incr_hi value does not need to be updated. the dco adder is 27 bits wide and the lsb of the incr register represents a step given by: min. step freq. = (40mhz/7) 3 2 2 27 = 4257475 millihertz and the output frequency is: freq. out = chx_carr_incr reg. value 3 min. step freq. the nominal value of the chx_carr_incr register for gps is 01f7 b1b9 h (to get a carrier at 1405396825 mhz when the gp1010 clock signal is at 40 mhz).
20 GP1020 register bit mapping bit description code_incr_hi 8 to 0 more significant bits of the code dco phase increment. code_incr_lo 15 to 0 less significant bits of the code dco phase increment. register operation the registers code_incr_lo and code_incr_hi are combined to form the 25 bits of the code_incr register, the code dco phase increment. both registers are write-only registers and can be written to at any time. the first write must be performed on code_incr_hi and the second write on chx_code_incr_hi & chx_code_incr_lo and all_code_incr_hi & all_code_incr_lo write addresses 02 & 03, 12 & 13, 22 & 23, 32 & 33, 42 & 43, 52 & 53 and 72 & 73 h chx_cntl and all_cntl read/write addresses 00, 10, 20, 30, 40, 50, and 70 h register bit mapping operation mode bit of chx_cntl reg. description (set by bit 15) 7 to 0 mode1 c/a code selection function 9 to 0 mode2 (see details below) 9 and 8 mode1 codesel(0:1):selects the apppropriate code to be shifted out of the dithering arm output of the code generator as follows: 9 = 0 8 = 0 early code 9 = 0 8 = 1 late code 9 = 1 8 = 0 dithering code 9 = 1 8 = 1 early minus late code 10 mode1&2 glo/gpsb: selects the code type to be generated. glonass c/a code when high, gps or inmarsat c/a code when low. 11 mode1&2 code_off/onb: when low, the code is output normally, but when high, the prompt, early and late codes are held high (no effect on the mixer outputs) and the early-minus-late code is held low to mask mixer outputs and force i&d input values to 0. 12 mode1&2 preset/updb: while high, programs the channel to preset mode, or while low, programs the channel to update mode. 14 and 13 mode1 not used - don?t care 14 and 13 mode2 codesel(0:1) as bits 9 and 8 mode1. 15 ?? mode: when low the cntl register is in mode1 (power up condition) and when high in mode2. when in mode1, the selection of a c/a code is done by selecting two taps of the g2 register, but in mode2 by presetting the value of the g2 register. the function of bits 8 and 9 will change depending on the mode. register operation chx_cntl can be written into at any time and any modifica- tion to its content is effective immediately (within 250 ns) while in update mode, or for all bits except preset/updb at the next tic while in preset mode. before reading the content of this register, it is necessary to wait 250 ns after the last write operation when in update mode. only the preset bit is available immediately but it is cleared 150ns after the preset sequence has taken place (at the tic following the initialisation of chx_20ms_epoch register). it is important to program this register first when starting a preset initialisation sequence. code_incr_lo. the written value is latched in the code_incr register on the trailing edge of a write to code_incr_lo. it is possible to perform a write only to code_incr_lo register if the code_incr_hi value does not need to be updated. the dco adder is 26 bits wide and the lsb of the incr register represents a step given by: min. step freq. = (40mhz/7) 3 2 2 26 = 85.14949 millihertz and the output frequency is: freq. out = chx_code_incr reg. value 3 min. step freq. note: the code dco drives the code generator to give half-chip time steps and so must be programmed to twice the required chip rate. this means that the chip rate resolution is 4257475 millihertz. the nominal value of the chx_code_incr register for gps is 016e a4a8 h (to get a chip rate of 1.023mhz when the gp1010 clock signal is at 40 mhz).
GP1020 21 c/a code selection the chx_cntl register allows two different modes of pro- gramming the code generator : mode 1: select the appropriate taps of g2 to generate the gps c/a code. mode 2: set the g2 register with the appropriate pat- tern to generate the gps or inmarsat c/a codes. note: when in mode 2, the g2 register should be loaded with a value representing its state at the time of the second chip. the difference between the two modes of programming the c/a code is that mode 2 allows the code generator to synthesise the 8 inmarsat c/a codes and mode 1 does not, but is more straightforward. the following table gives the pattern of bits 3 to 0 or 7 to 4 to select a particular tap (used in mode 1 of the chx_cntl register) : bit tap pattern 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1xx0 9 1xx1 10 the table below shows the bit setting required to select the appropriate taps which will decode the 37 possible gps prn signal numbers when in mode 1 and the bit setting required to set the g2 register in the second chip state for all gps and inmarsat c/a codes when in mode 2. note that the list does not show all the possible tap and bit setting combinations. tap combinations which are not listed can also be used if required. gps prn mode 1 selected mode 2 signal no. bit setting taps bit setting 7 to 0 9 to 0 1 0001 0101 2 exor 6 3f6 h 2 0010 0110 3 exor 7 3ec h 3 0011 0111 4 exor 8 3d8 h 4 0100 1xx0 5 exor 9 3b0 h 5 0000 1xx0 1 exor 9 04b h 6 0001 1xx1 2 exor 10 096 h 7 0000 0111 1 exor 8 2cb h 8 0001 1xx0 2 exor 9 196 h 9 0010 1xx1 3 exor 10 32c h 10 0001 0010 2 exor 3 3ba h 11 0010 0011 3 exor 4 374 h 12 0100 0101 5 exor 6 1d0 h 13 0101 0110 6 exor 7 3a0 h 14 0110 0111 7 exor 8 340 h 15 0111 1xx0 8 exor 9 280 h 16 1xx0 1xx1 9 exor 10 100 h 17 0000 0011 1 exor 4 113 h 18 0001 0100 2 exor 5 226 h 19 0010 0101 3 exor 6 04c h 20 0011 0110 4 exor 7 098 h 21 0100 0111 5 exor 8 130 h 22 0101 1xx0 6 exor 9 260 h gps prn mode 1 selected mode 2 signal no. bit setting taps bit setting 7 to 0 9 to 0 23 0000 0010 1 exor 3 267 h 24 0011 0101 4 exor 6 120 h 25 0100 0110 5 exor 7 270 h 26 0101 0111 6 exor 8 0e0 h 27 0110 1xx0 7 exor 9 1c0 h 28 0111 1xx1 8 exor 10 380 h 29 0000 0101 1 exor 6 22b h 30 0001 0110 2 exor 7 056 h 31 0010 0111 3 exor 8 0ac h 32 0011 1xx0 4 exor 9 158 h 33 0100 1xx1 5 exor 10 2b0 h 34 * 0011 1xx1 4 exor 10 058 h 35 0000 0110 1 exor 7 18b h 36 0001 0111 2 exor 8 316 h 37 * 0011 1xx1 4 exor 10 058 h 201 n/a n/a n/a 2c4 h 202 n/a n/a n/a 10a h 205 n/a n/a n/a 3e3 h 206 n/a n/a n/a 0f8 h 207 n/a n/a n/a 25f h 208 n/a n/a n/a 1e7 h 209 n/a n/a n/a 2b5 h 211 n/a n/a n/a 10e h *c/a codes 34 and 37 are common note: prn sequences 33 to 37 are reserved for other uses (e.g. ground transmitters). the table below lists the required setting of the register bit 0 to generate the glonass c/a code or the glonass-like test c/a code. note that bit 10 must be high to select glonass rather than gps codes. bit 0 setting code type selected g1 taps mode 1 & 2 0 glonass 5 exor 9 1 glonass test 3 exor 5 exor 6 exor 9 in update mode, the c/a code generated by the code generator can be changed at any time but the next accumu- lated data following the command will not be valid. the mode bit cannot be modified without disabling the clock phases when in update mode otherwise the c/a code generated will not be valid. this is not the case when starting a preset sequence. to provide a clean switch between glonass and gps modes of operation for a specific channel, it is necessary to proceed as follows: disable propagation of the clock phases to this tracking channel by selecting the appropriate bit in the reset_cntl register, then select the desired mode of opera- tion glonass or gps and re-enable the propagation of the clock phases. if the clock phases propagation are not disabled, the next accumulated data will not be valid. when the dithering code has been selected, the dithering arm will use the early code for a period of 20 c/a codes, the late code for the next 20 c/a codes and this process of dithering between early and late code will be repeated indefinitely. the dithering arm will use the early code for the first 20 ms epoch following a slew or a preset operation. upon masterreset, chx_cntl bits are set to the states given in the following table.
22 GP1020 bit state description 7 to 0 03 h gps prn no. 17 selected. 9 and 8 00 early code on the dithering arm. 10 0 gps c/a code 11 0 code on 12 0 update mode 14 and 13 00 n/a (mode1) 15 0 mode1 chx_code_slew and all_code_slew write addresses a2, a6, aa, ae, b2, b6 and be h register bit mapping bit description 10 to 0 unsigned integer ranging from 0 to 2047 representing the number of code half chips to be slewed after the next dump if in update mode or after the next tic, if in preset mode. since there are only 2046 half chips in a gps c/a code, a programmed value of 2047 is equivalent to a programmed value of 1 but the next dump event will take place 1 ms later. for the glonass code a similar wrap- around will occur at 1023 and 2045. the chx_code_slew register can be written to at any time. if two accesses have taken place before a dump in update mode or before a tic when in preset mode, the latest value will be used at the next slew operation. when the slew process is being executed, a write access to the chx_code_slew register will cause the transfer of this new value into the counter and will be used immediately. the result is not predictable. this situation should be avoided by synchronising the access with the associated chx_new_accum_data status bit. slew timing details are shown in figs. 14 and 15. t 1 dump: time fig. 14 slew in update mode 1021 1022 1023 1 1 1 2 3 ? ? ? ? ? ? ? 1023 chips 1025 chips c/a code chip no. : t 1 : load 4 in the chx_code_slew register = 2 chips delay. dump: time fig. 15 slew in preset mode 98 99 100 1 1 1 2 3 ? ? ? ? ? ? ? 1023 chips 10245 chips c/a code chip no. : t 1 : set the preset mode (bit 12 in chx_cntl register) t 2 : load 3 in the chx_code_slew register (=15 chips delay) t 3 : tic event t 1 t 2 t 3 4
GP1020 23 chx_i_dith, chx_q_dith, chx_i_prompt, chx_q_prompt 24 consecutive read addresses 84 to 9b h register bit mapping bit description 15 to 2 accumulated data registers, which are loaded on each dump event with the i&d accumulator results. 1 not used, held low. 0 instantaneous value of the over/underflow flag (for test purposes). normally low, but high if the data being accumulated in the i&d accumulator has reached the over/underflow condition. register operation these registers are read only registers; they can be read at any time and their content is protected by the overwrite protection mechanism of accumulated data. the chx_i_prompt and chx_q_prompt contain the accumulated data taken on the prompt arm. the chx_i_dith and chx_q_dith contain the accumulated data taken on the dithering arm. the overwrite protection mechanism is released by reading the chx_q_prompt register. the values contained in the registers are 2?s complement values with the valid range of the data from 2 13 for negative numbers to (2 13 2 1) for positive numbers. when an over/ underflow condition is flagged (chx_ovfl_accum bit in accum_status_b set high) the contents of the registers for this arm will be the last i&d accumulator values before the over/ underflow condition happened. if bit 15 is low it is an overflow and if bit 15 is high it is an underflow. bits 0 of the 24 accumulated data registers have no link with the other data in these registers. when high, each of these bits indicates that the data being accumulated in the i&d has reached the maximum value (positive or negative) of the accumulator and this value will be available at the next dump. chx_meas_rst and all_meas_rst write addresses 84, 88, 8c, 90, 94, 98 and 9c h a write to this location with don?t care data resets all measure- ment data status bits contained in both meas_status_a and meas_status_b registers. it also clears any active overwrite protection on measurement data. all_meas_rst access will also clear the mark_fb_ack and the rtc_tic_ack flags in meas_status_a register and the associated overwrite pro- tections. chx_preset_phase and all_preset_phase write addresses a1, a5, a9, ad, b1, b5 and bd h register bit mapping bit description 7 to 0 most significant bits of the code dco phase which is to be loaded at next tic event if in preset mode. register operation in preset mode, the 8 bits of the preset_phase register are added to the top 7 bits of the chx_code_incr register chx_epoch_a read addresses a0, a4, a8, ac, b0, b4 h this register contains the variables as detailed below. register bit mapping bit description 15 to 11 chx_1ms_epoch: the one millisecond epoch counter value sampled at tic event. its valid range is 0 to 19. 10 to 0 chx_code_phase: represents the code phase of the code generator when sampled and latched on a tic, expressed as a number of half code chips. it ranges from 0 to 2045 when a gps c/a code is generated and from 0 to 1021 when a glonass c/a code is generated. chx_epoch_a content is protected from overwrite by the overwrite protection mechanism of measurement data. chx_epoch_b read addresses a1, a5, a9, ad, b1, b5 h the register contains two variables as detailed below: register bit mapping bit description 15 and 14 not used. 13 to 8 chx_20ms_epoch: contains the 20 millisecond epoch counter value sampled at tic event. its valid range is from 0 to 49. 7 to 0 chx_code_dco_phase: contains the eight most significant bits of the code dco phase accumulator sampled at tic event. the weight of the least significant bit is 2 p /256 radians, 2 p being 1/2 code chip. the byte is an unsigned integer valid from 0 to 255. chx_epoch_b content is protected from overwrite by the overwrite protection mechanism of measurement data. chx_epoch_chk read addresses 02, 12, 22, 32, 42, 52 h this register contains the instantaneous value of chx_1ms_epoch and chx_20ms_epoch. it can be used to verify if the epoch counters have properly been initialised by the software since the timing is critical for the initialisation operation. its value is not latched and is updated on the occurence of a dump. this register should be read only when there is no possibility of getting a dump during the read cycle. register bit mapping bit description 15 to 13 not used. 12 to 8 instantaneous value of chx_1ms_epoch. 7 bit 14 of chx_cntl (test purpose only) 6 cnttestmode bit 5 to 0 instantaneous value of chx_20ms_epoch.
24 GP1020 and the sum is loaded into the 8 bits of the code_dco accumulator along with all zeros in the lower bits. the preset_phase register is a write only register and it can be written to at any time in preset mode or in update mode. the weight of the least significant bit of preset phase is 2 p /256 radian of a half chip cycle. chx_shift_reg read addresses 03, 13, 23, 33, 43, 53 h register bit mapping bit description 15 to 13 not used; don?t care data 12 bit 15 (mode bit) of chx_cntl (test purpose only) 11 11th chip 10 12th chip 9 first chip 0 10th chip register operation this register is used for test purpose only. the 12 less significant bits of the word contain the first 12-bit sequence of the c/a code issued by the channel?s code generator on the dither- ing arm. the latching process is armed as a result of a completed slew operation, a preset sequence or a clock phase release by chx_rstb bit of the reset_cntl register. it is necessary to wait at least 24 code dco clock cycles (12 m s in gps mode and 24 m s in glonass mode) before reading this register. the 3 most significant bits of the word are don?t care data. when in early minus late mode, this register will contain the first 12-bit sequence of the code sign issued on the dithering arm. the following table contains the result of the shift_reg register for all possible cases. shift_reg value gps/ glonass c/a code early/late early-minus-late code code 1 f20 h 640 h 2 f90 h a40 h 3 fc8 h 241 h 4 fe4 h 242 h 5 25b h 249 h 6 32d h 24a h 7 e59 h 248 h 8 72c h 648 h 9 b96 h a4a h 10 b44 h 689 h 11 fa2 h 289 h 12 7e8 h a82 h 13 bf4 h 294 h 14 ffa h 290 h 15 ffd h 609 h 16 7fe h 229 h 17 26e h 222 h 18 b37 h 221 h 19 79b h 225 h 20 3cd h 228 h 21 3e6 h 620 h shift_reg value gps/ glonass c/a code early/late early-minus-late code code 22 bf3 h a12 h 23 e33 h 610 h 24 7f6 h 249 h 25 fe3 h 205 h 26 7f1 h 621 h 27 3f8 h 608 h 28 bfc h 242 h 29 a57 h a50 h 30 72b h a52 h 31 395 h 254 h 32 3ca h 250 h 33 be5 h 649 h 34 * 7cb h 648 h 35 25c h 244 h 36 b2e h 245 h 37 * 7cb h 648 h 201 bb9 h 222 h 202 35e h 684 h 205 a70 h a10 h 206 3c1 h 208 h 207 a0b h a08 h 208 630 h 610 h 209 aa5 h aa4 h 211 71e h a04 h glonass 3f8 h 201 h glonass ff8 h 610 h _test * note c/a codes 34 and 37 are the same. chx_sig_sel and all_sig_sel write addresses 01, 11, 21, 31, 41, 51 and 71 h register bit mapping description signal source bit selection with the selected input port following encoding: bit 3 2 1 0 3 to 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 x 0 0 8 1 x 0 1 9 1 x 1 0 self test signal 1 x 1 1 ground 15 to 4 not used, don?t care. register description chx_sig_sel can be written into at any time. the self test signal is the sign and mag outputs (tsign and tmag output pins) of the self_test_generator block and are wrapped round internally.
GP1020 25 chx_1ms_epoch and all_1ms_epoch write addresses a0, a4, a8, ac, b0, b4 and bc h these registers are write-only registers. their operation is affected by the current channel mode, preset or update. in update mode, the data being written into these registers is immediately transferred to the 1 ms epoch counter. in preset mode however, the data is transferred only after the next tic. refer to section 7 of detailed operation of the GP1020 for more details of the preset mode. register bit mapping bit description 4 to 0 contains the 1ms epoch counter value to be loaded. its valid range is from 0 to 19. 15 to 5 don?t care chx_20ms_epoch and all_20ms_epoch write addresses a3, a7, ab, af, b3, b7, and bf h these registers are write-only registers. their operation is affected by the current channel mode, preset or update. in update mode, the data being written into 20ms_epoch is immediately transferred to the 20 ms epoch counter. in preset mode however, the data is transfered only after the next tic. it is important to load the 20ms_epoch register last in the preset mode loading sequence because the trailing edge of a write to this register enables the preset operation on the next tic. refer to section 7 of detailed operation of the GP1020 for more details of the preset mode. the chx_20ms_epoch contains a test control bit (cnttestmode) which is used to test different counters in the channels. when active this bit selects a 57 mhz clock (clk 2) to drive the 20ms_epoch counter and replace the codeclk signal by the tck8 input signal, also tck8 will drive the code generator, the code_slew and code_phase counters, and finally, it will allow the code generator to be set to the 1023rd chip position by a write operation to the chx_accum_reset location and to write into the chx_tst_code_phase and chx_tst_cycle registers. register bit mapping bit description 15 to 7 not used 6 cnttestmode: normal mode when low. this bit is set low by a master reset and should normally always be programmed low. when high, the code generator, the 20ms_epoch, code_phase, code_slew and carrier_cycle counters are in test mode. 5 to 0 contains the 20 ms epoch counter value to be loaded. its valid range is from 0 to 49. down_count_hi and down_count_lo write addresses c3 and c4 h these two registers are used to program the time mark generator. refer to section 11 of detailed operation of the GP1020 (page 31) for more details of the principle of operation of the time mark generator. chx_tst_code_phase and all_tst_code_phase write addresses 06, 16, 26, 36, 46, 56 and 76 h this location can be written into only if the cnttestmode signal, in the chx_20ms_epoch is high and if the msb of the code_dco phase is low (power up condition). the chx_tst_code_phase is an unsigned 11 bit write only register. it is used to pre-load the code_phase counter with a specific value. all_tst_code_phase operates only on those channels with cnttestmode set high. register bit mapping bit description 10 to 0 11 bits of the code_phase counter chx_tst_code_slew read addresses 01, 11, 21, 31, 41, 51 h this location can be read at anytime for test purposes. it gives access to actual contents of chx_code_slew counter. it is possible to read unstable data if the counter value is changing during the read pulse. register bit mapping bit description 15 to 13 don?t care 12 bit 13 of chx_cntl register (test purpose only) 11 indicates the state of the code_slew counter (for test purpose): 0: has reached the count of zero 1: counter value is not zero and/or the counter is not enabled to count (see note) 10 to 0 contents of chx_code_slew note : the code_slew counter is enabled to count when it has been loaded (chx_code_slew register) and a dump has occured if in update mode. in preset mode, the counter is loaded and enabled to count upon a tic event if the chx_20ms_epoch had been loaded. chx_tst_cycle and all_tst_cycle write addresses 07, 17, 27, 37, 47, 57 and 77 h this location can be written into only if the cnttestmode signal, in the chx_20ms_epoch is active (high) and if the msb of the carrier_dco phase is low (as at power up). the chx_tst_cycle is an unsigned 16-bit write only register. it is used to pre-load the carrier_cycle counter with a specific value. the carrier_counter is an 18-bit counter; the two less significant bits will be set to 0 when writing into chx_tst_cycle. all_tst_cycle operates only on those channels whose cnttestmode bit is high. register bit mapping bit description 15 to 0 16 msb bits of the carrier_cycle counter
26 GP1020 down_count_lo is programmed with a 16-bit unsigned integer word, with valid range from 0 to ffff (hex). down_count_hi is programmed with a 5-bit unsigned integer word, with valid range from 0 to 01f (hex). the concatenated value of both registers represents the time delay, less 25 nanoseconds, from the next tic to the time mark output signal in units of 50 nanoseconds. the trailing edge of a write to down_count_lo arms the time mark generator. when the next tic occurs, the time mark counter is loaded and then decrements until it reaches zero, at which instant the time mark is output. meas_status_a read addresses 80 h register bit mapping bit description 0 ch1_new_meas_data 1 ch2_new_meas_data 2 ch3_new_meas_data 3 ch4_new_meas_data 4 ch5_new_meas_data 5 ch6_new_meas_data 6 not used 7 not used 8 not used 9 not used 10 not used 11 not used 12 not used 13 not used 14 mark_fb_ack 15 rtc_tic_ack register description meas_status_a is located at an address contiguous with accumulated data status registers so that it can be read in the same read block operation. the status bits of this register are sampled and latched on the positive edge of every int out or int in signal. they can also be sampled and latched on request by performing a write operation to status_latch location. bit description chx_new_meas_data status bit active high indicates if there is new measurement data available to be read. each individual bit can be cleared by a write operation with don?t care data to chx_meas_rst. this operation releases the overwrite protection. each bit is also cleared on the trailing edge of a read of the associated chx_carr_cycle register. if new accumu- lated data becomes available after status bits have been latched, the overwrite protection is not cleared while reading the chx_carr_cycle register and the chx_new_meas_data bit will be set at the next meas_status_a. a master reset (hardware or software) and the inhibition of clock phases will also clear this status bit. rtc_tic_ack status bit is set whenever a real time clock interrupt has been received and the 100ms_tic or 9ms_tic following the interrupt has occured. it is reset by a read of rtc_delay register or an all_meas_rst command. rtc_delay is overwrite protected by the measurement data protection mechanism. mark_fb_ack status bit is set whenever a time mark feedback signal has been received on the selected pin, mark_fb1, mark_fb2 or mark_fb3 or by the selected edge of the tic out signal. it is reset by a read of prop_delay_lo register or a all_meas_rst command. mark_fb_ack is overwrite protected by the measurement data protection mecha- nism. rtc_tic_ack and mark_fb_ack status bits are cleared by a hardware master reset. a software master reset does not affect the time base generator block, where these two flags are generated. meas_status_b read address 81 h register bit mapping bit description 0 ch1_missed_meas 1 ch2_missed_meas 2 ch3_missed_meas 3 ch4_missed_meas 4 ch5_missed_meas 5 ch6_missed_meas 6 not used 7 not used 8 ch1_slew 9 ch2_slew 10 ch3_slew 11 ch4_slew 12 ch5_slew 13 ch6_slew 14 not used 15 not used register description meas_status_b register is located at an address contigu- ous with accumulated data status registers so that it can be read in the same read block operation. the status bits of this register are sampled and latched on the positive edge of every int out or int in signal. they can also be sampled and latched on request by performing a write operation to status_latch location. bit description chx_missed_meas: status bit active high indicating if there has been missed measurement data resulting from a too long delay (> tic period) before the measurement data specific to this channel was either read or the chx_new_meas_data bit was cleared. this bit is set on a tic and latched until either a master reset (hardware or software) or until a write operation to chx_meas_rst chx_slew: status indicating if the code phase counter was being slewed at time of tic sampling. if such is the case, the measurement data is not reliable. this bit is updated at each tic when the overwrite protection is not active and is reset whenever chx_meas_rst is written into with don?t care data or upon a master reset (hardware or software). all status bits in this register will also be cleared when the clock phase propagation is disabled. prop_delay_lo and prop_delay_hi read addresses c3 and c4 h register bit mapping, prop_delay_lo bit description 15 to 0 16 less significant bits of down counter register bit mapping, prop_delay_hi bit description 4 to 0 5 more significant bits of down counter. 15 to 5 don?t care, held low.
GP1020 27 prop_delay_lo is a 16-bit register containing the 16 less significant bits of an unsigned integer prop_delay whose value is the number, minus one, of 50 nanosecond intervals completed since the mark output signal was generated. prop_delay_hi is a 5-bit register containing the 5 more significant bits of the same integer. this integer comes from the mark output programmable down counter and the down_count register as detailed below. if a read access is performed when the programmable down counter is working the data may be not stable. a mark_fb_ack status bit should be acknowledged before performing a read access to the prop_delay registers. the programmable down counter operates as follows: time counter contents remarks ta down_count the counter is loaded by software with down_count value. tb the one second time mark signal is issued and prop- agates through the output driver. the down counter wraps round and continues to count down. tc prop_delay when the feedback signal at input pin mark fb1, mark fb2, mark fb3 or internal tic signal, as selected by bits 7 to 5 of the timer_cntl register, reaches the down counter, its value is frozen and can be read by the processor, (16 lower bits only) to get the correct number of 50 ns intervals, 1 should be added to the prop_delay number. for example, if the feed- back was so fast that the counter did not have time to count, the prop_delay value will be 1f ffff h and by adding 1 the result becomes 00 0000 h . other examples of delay counts: prop_delay value real number of 50 ns intervals 00 0000 h 1 00 0001 h 2 1f fffc h 2,097,150 if there is no feedback coming from the external driver, a time- out function will stop the counter and no mark_fb_ack status bit will be asserted. the prop_delay value will be 1f fffd h (representing a propagation delay of 104.8575 ms). the prop_delay value can be used for: 1. computation of down_count, to compensate for the propagation delay in the output driver circuit if this delay islarger than 50 nanoseconds. 2. as a bite function, to check that the time_mark output drivers work or to verify the tic period. reset_cntl read/write address c0 h register bit mapping bit description 0 mrb (chip masterreset) 1 ch1_rstb 2 ch2_rstb 3 ch3_rstb 4 ch4_rstb 5 ch5_rstb 6 ch6_rstb 7 to 15 not used bit description chx_rstb: when active low, the reset bit inhibits propa- gation of the clock phases to the tracking channel and resets the code generator, accumulated and measurement flags, code_dco and carrier_dco accumulators and their as- sociated incr registers, the i&d accumulators, the code slew counter and finally the code phase counter. this is required for the search algorithm of one satellite signal using many channels in order to start from a known relative code phase on all the channels. however, all of the registers in chx can be pro- grammed and read as usual. to restart normal operation in the different channels at the same time, the corresponding chx_rstb bits should be set to high during the same write operation. all chx_rstb are set low by a master reset. mrb: when low (software reset), the effect is identical to the hardware masterreset except that the clock generator and the time base generator are not affected. it should be set to high to allow access to the different registers. mrb is set high by a hardware master reset. rtc_delay read address c2 h register bit mapping bit description 15 to 0 number of clock intervals counted from the occurrence of an rtc interrupt and the next tic (tic in if the external source is selected). each count represents 2.275 microsecond. the register content is unsigned and the validity range is from 0 to tic period/2.275 microsecond. the error in rtc_delay is 6 2.275 microsecond as shown in fig. 16. rtc_delay is latched on a tic and is overwrite protected by its own measurement data overwrite protection mechanism. the rtc_tic_ack status bit of meas_status_a register indicates if an rtc interrupt has been received. the rtc_tic_ack status bit is cleared by writing to the all_meas_rst address and also by reading rtc_delay register.
28 GP1020 stat_chk_sel write address c5 h register bit mapping description signal source bit selection with the selected input port following encoding: bit 3 2 1 0 3 to 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 x 0 0 8 1 x 0 1 9 1 x 1 0 self test signal 1 x 1 1 ground 15 to 4 not used, don?t care. register description stat_chk_sel can be written into at any time. the self test signal is both the sign and magnitude outputs (tsign and tmag output pins) of the self_test_generator block and are connected internally. stat_chk_sign and stat_chk_mag read addresses c5 and c6 h register bit mapping bit description 13 to 0 unsigned integer ranging from 0 to 16383 representing the number of sign or magnitude bits sampled during two interrupt time base periods. 15 to 14 don?t care, held low. these registers are overwrite protected. the overwrite protection is released and the new_stat_data bit of the accum_status_a is reset on the trailing edge of a read to stat_chk_mag or a write operation to all_accum_reset location. therefore, stat_chk_mag should be read after stat_chk_sign. for the first time the flag new_stat_data is set after a master reset, if a write to the stat_chk_sel register has not been performed within two interrupt time base (int) periods, non valid data will be latched in stat_chk_sign and stat_chk_mag registers. for this reason perform a dummy read to stat_chk_mag in order to clear the flag and wait for the next time the flag is set to get valid data. note: the stat_chk_mag register contains the number of samples having the values 1 3 or 2 3, and the stat_chk_sign register contains the number of positive samples (1 or 3) from the selected input port. status_latch writeaddress 80 h a write to this location with don?t care data latches the state of all status bits contained in accum_status_a, accum_status_b, meas_status_a and meas_status_b. performing a write to status_latch prior to reading the status registers ensures reading of stable status values. the latch takes effect within 200 nanoseconds of the leading edge of the write pulse. the low to high transition of the int signal will also latch the state of the status bit, thus it is not necessary to write to status_latch when the status registers are to be read as a response to the int signal in an interrupt handling routine. the write to status_latch is required only when the status registers are read at ?random? times, controlled by the microprocessor. these two mecha- nisms are mutually exclusive and should not be used in conjunc- tion - if they are both used (a write to status_latch after the occurance of an int signal) contentions and confusion will result. to avoid this, make sure a read access does not take place at the same time as an interrupt rising edge. if the int_maskb bit in timer_cntl register is not set to high, the interrupt will not latch the status bits in the status registers accum_status_a, accum_status_b, meas_status_a and meas_status_b but a status_latch write access will do so. also, when a GP1020 is configured as a slave, it should have the int_source and the int_maskb bits in the timer_cntl register set to high to get the status bits sampled at the same instant in both master and slave GP1020s. tdata_duty_cycle write address c8 h this register is associated with the self_test_generator. it allows selection of the duty cycle of the data inversion function. the time base period is 11 c/a code chips. the value of tdata_duty_cycle, valid from 0 to 10, determines the number of chips within the time base period where the data bit modulating the self test signal will be inverted. when the self test signal is fed back in a tracking channel, the inversion causes a slope reversal in the accumulator of the accumulate and dump module and prevents the accumulator from saturating over a code epoch when tdata_duty_cycle is properly set. this is the same effect as noise on a real satellite signal. register operation this register is a write only register and can be written into at any time. at power up the register is reset, so it will always select the data inversion function. if the bits are all 1 the data inversion rtc_int time fig. 16 next 2275 m s clock edge (free running) up to 2275 m s delay makes count too high previous 2275 m s clock edge tic up to 2275 m s delay makes count too small
GP1020 29 function will never be selected. for standard operation a single 0 is required and all the other bits must be at 1. the position of the 0 in the register allows the duty cycle of the data inversion function to be set as shown below: bits 10 9 8 7 6 5 4 3 2 1 0 description 0 0 0 0 0 0 0 0 0 0 0 power up condition, the data inversion function is always selected. 1 1 1 1 1 1 1 1 1 1 0 the data inversion function is always selected. 1 1 1 1 1 1 1 1 1 0 1 the data inversion function is selected 10 times in 11. 1 1 1 1 1 1 1 1 0 1 1 the data inversion function is selected 9 times in 11. 0 1 1 1 1 1 1 1 1 1 1 the data inversion function is selected 1 time in 11. 1 1 1 1 1 1 1 1 1 1 1 the data inversion function is never selected. timer_cntl write address c2 h register bit mapping bit name description 0 tic_period when low, the tic period is 175 ns 3 571,428 = 999999ms. when high, the tic period is 175 ns 3 51,948 = 90909ms. tic_period is set low by reset. 1 int_maskb when low, the interrupt output signal is disabled, the int out pin is held low and the status bits are not sampled by an on- chip or an externally generated interrupt. when high, the int- errupt output signal is enabled and the status bits will be sampled by an interrupt. int_mask is set low by reset. 2 tic_source when low, tic source is internal, when high, tic source is external (provided by a companion GP1020 through ticin pin). tic_source is set low by reset. register bit mpping bit nme description 3 int_source when low, the signl used to ltch the stte of sttus bits nd the results of the stat_check block is the positive edge in intel mode or the negtive edge in motorol mode of the int signl generted on-chip. when high, the edge of the int signl provided on intin pin of the device by compnion GP1020 is used insted. int_source is set low by reset. 4 test_op/markb when low, the GP1020 mark output pin will output the time mark output. when high, the output will be driven by signl selected by the ch1_dump/osc_check bit (bit 8) of this timer_cntl register. test_op/markb is set low by reset. 7 to 5 mrk feedbck ctive edge selection, with the following encoding: bit selected 7 6 5 function 0 0 0 fb1 - 0 0 1 fb1 0 1 0 fb2 - 0 1 1 fb2 1 0 0 fb3 - 1 0 1 fb3 1 1 0 ticout - 1 1 1 ticout the fbx - (rising edge) nd fbx (flling edge) signl edges re used to clculte the pulse width of the mrk feedbck signl. this clcul- tion llows monitoring of the pulse width nd verifiction tht the result is in ccordnce with the 1 ms 0.01 ms specifiction. the tic out signl is lso vilble s feedbck for test purposes. bits 7 to 5 re set low by reset.
30 GP1020 register bit mapping bit name description 8 ch1_dump/osc when low the GP1020 mark output pin will output a square wave with a period of 455 microseconds. (40mhz/182). because this clock is derived from the tcxo, its stability and accuracy is representative of the tcxo stability and accuracy. when high, the GP1020 mark output pin will output a square-wave chang- ing its level at each dump event in channel 1. these features are used for test purposes during atp of the gps sensor unit and the test_op/mark bit (bit 4) must be set to high to get either of these two test outputs.ch1_dump/ osc_check is set low by reset. 12 to 9 interrupt time base selection with the encoding given in the following table. bit 12 11 10 9 selected interrupt high time low time timebase period ( m s) ( m s) ( m s) 0 0 x x 505.050 252.525 252.525 0100 420.875 84.175 336.700 0101 505.050 252.525 252.525 0110 589.225 336.700 252.525 0111 673.400 336.700 336.700 1000 757.575 420.875 336.700 1001 841.750 420.875 420.875 1010 925.925 505.050 420.875 1011 1010.100 84.175 925.925 1100 1094.275 168.350 925.925 1101 1178.450 84.175 1094.275 1110 1262.625 168.350 1094.275 1111 1346.800 420.875 925.925 bits 12 to 9 are set low by reset. _check
GP1020 31 detailed operation of the GP1020 1. master reset - hardware or software. at master reset, all registers, accumulators and counters are cleared except chx_cntl. in particular, this implies the follow- ing initial states: all chx_rstb bits of the reset_cntl register are cleared. thus all tracking channel clock phases are disabled. program- ming registers can take place either before or after releasing the chx_rstb bits. all the tracking channels are in update mode, the satellite code selected is gps prn no. 17 and the early code is selected on the dithering arm. all chx_cntl registers are in mode 1. the tic generator will be free running at start-up with a 100ms tic period setting. the int_maskb bit of the timer_cntl register is low, therefore the int_out signal will be disabled and the output pin held low. the interrupt time base is set to 505.05 m s. the bitecntl bit of the bite register is reset low (inactive state). the associated bitecntl output pin is also low. the data bus is forced into input mode to avoid contention at power up. 2. search operation at power up, after a power glitch, or after losing satellite signals. register initialisation for each channel, the proper gps or glonass signal source has to be selected by writing the proper code into chx_sig_sel registers. the contents of these registers can be changed at any time during the operation to change the signal sources for any channels. at power up, all chx_rstb bits of the rst_cntl register are in the reset low state. as stated above, in that state, all tracking channel control registers can be programmed. when it is required to perform a search for one satellite with more than one channel, these channels are first reset if not already in that state, with the corresponding chx_rstb bits, then the control registers are programmed. in particular, each code_slew register is programmed with a different value. then, the chx_rstb bits are released, causing the channels to start operating at the same time with the same code phase. one millisecond later, all channels will get the same accumulated data and will be slewed with the pre-programmed values and will continue with a known relative code phase difference. note that every time chx_rstb is set low, the code generator is reset. the following additional initialisation operations have to be performed. the block write addresses can be used whenever appropriate. carrier_dco programming the carr_incr_hi and the carr_incr_lo registers are programmed in sequence with the relevant data according to the estimated doppler shift for the frequency bin being looked at. the programming is effective as soon as the write operation to carr_incr_lo is completed (in fact, a small delay of 175 ns maximum will occur to allow synchronisation of the processor write operation to the chip operation). if the content of carr_incr_hi does not need to be modified, it is not neces- sary to write into it. it is always necessary to write into carr_incr_lo in order for the programming to be effective. note that, typically, the search algorithm would dwell on a given frequency bin and perform a search over all code phases. then it would repeat the process for the next frequency bin. code_dco programming the tracking channel being in update mode, the preset_phase register does not need to be programmed. the code_incr_hi and the code_incr_lo registers are programmed in sequence with the relevant data according to the estimated doppler shift. given that the chx_rstb bit of the reset_cntl register is inactive, the programming is effective as soon as the write operation to code_incr_lo is completed. if the content of code_incr_hi does not need to be modified, it is not necessary to write into it. it is always necessary to write into code_incr_lo in order for the programming to be effec- tive. code generator programming 1. select in chx_cntl register the type of code to be used in the dithering arm of the correlator; normally, for a search opera- tion, either an early or a late code is selected. the preset/ updb bit will be set low, for example, in update mode by master reset. 2. select in chx_cntl register the code to be generated among the 45 possible c/a codes or the unique glonass code. (actually, all possible code combinations are programmable even those not used by the gps constellation and some glonass-like codes are also available.) the selected code is applicable to both the prompt and the dithering arm. 3. program each tracking channel code_slew register with the desired code phase. the slew operation will become effec- tive at the first dump e.g. about 1 ms after chx_rstb release. the first dump will generate don?t care accumulated data and will set the associated chx_new_accum_data status bit. the second and the following dumps will generate useful data. 4. release the relevant chx_rstb bits of the reset_cntl register in order to start operation of the tracking channels. when channels of more than one GP1020 are being used to search for the same code, consecutive write operations to each chip?s reset_cntl register should ensure a startup with reasonably well known relative code phases between the two chips. whenever the code clock is being inhibited (to slew the code phase), the accumulate & dump module is held reset. it will start to accumulate correlation results only after the slew operation is completed. 3. reading the accumulated data every time a dump occurs, the corresponding chx_new_accum_data status bit is set in the accum_status_a register. all in-phase and quad-phase registers together with accum_status_a and accum_status_b registers are mapped in consecutive ad- dresses so that they can be block-read after every timebase interrupt. alternatively, a polling technique can be used by periodically reading the accum_status_a register to find if an interrupt or a write into status_latch has been per- formed. the data contained in the in_phase and quad_phase registers of the prompt and dithering arms will be protected from an overwrite due to consecutive dump events. the protection mechanism is released on the trailing edge of a read operation of the q_prompt register. thus the order of reading i_dith, q_dith and i_prompt is optional but q_prompt must always be read last to ensure coherence of the data set and to release the overwrite protection mechanism. the chx_missed_accum bit of the accum_status_b register indicates new accumulated data has been missed because of a too long response time for reading the accumulated data. this status bit, when set, is latched until it is cleared by a write operation to chx_accum_reset or by a master reset or by chx_rstb set to low. 4. search on other code phases when it is desired to correlate on the next code phase, the code_slew has to be programmed with a value of 2 (in units
32 GP1020 of half code chips). the slew will be effective on the next dump. thus this dump will generate don?t care accumulated data and as a minimum, the q_prompt register will have to be read to release the overwrite protection mechanism. note that it is only possible to delay the phase of the code. it cannot be advanced. 5. data bit synchronisation related operations when the right code phase is found, the carrier loop is closed. the carr_incr_hi and carr_incr_lo registers can be reprogrammed at any time to close the feedback loop and resume code tracking. the data bit sync algorithm should find the data bit transition instant. the processor calculates the present one millisecond epoch and programs this value into the 1ms_epoch register. the effect is immediate. after each dump, the epoch counter value can be read within 1ms and preferably at the same time as the integrate and dump registers. this provides a means of verifying that the epoch counters are indeed properly programmed. programming the epoch counter in the 500 m s period following a valid chx_new_accum_data should ensure that the program- ming becomes effective before the next dump. alternatively, the epoch registers can be left free-running and the delta-epoch can be added by the software each time it reads the epoch registers. however, the dithering between early and late code will be controlled by the actual contents of the epoch registers, which will not necessarily be in phase with data bit boundaries. 6. reading the measurement data at every occurrence of a tic, the measurement data is latched in measurement data registers. the tic does not generate any interrupt signal, however, it does set the chx_new_meas_data status bits of the meas_status_a register. this register is normally always read while collecting accumulated data once every 505.05 microseconds (the int out signal rate). the software tests the chx_new_meas_data status bits to determine if new meas- urement data is available to be read. for each channel, the last measurement data register to be read must be chx_carr_cycle because the trailing edge of this read releases the overwrite protection mechanism and clears the corresponding chx_new_meas_data bit. the software must also read the meas_status_b register to determine if there was any missed measurement data or if phase and epoch counters were being slewed during the last tic period, indicating invalid measurement data for the affected channel. 7. the preset mode each tracking channel can be individually programmed to operate either in update or preset mode. a given channel is programmed in preset mode by writing a high into the preset/updb bit of the chx_cntl register. the sequence of operations is as follows: 1. write into chx_cntl to select the preset mode together with the appropriate code, code format on the dithering arm, etc. since the preset mode is selected, the new selected code and code format will be effective on the next tic. 2. between the instant at which the preset mode is selected and the next tic, the tracking channel will continue to operate normally, that is, it will provide accumulated data for the signal being tracked. 3. the increment registers of the code and carrier dco?s have to be loaded with the appropriate frequencies for the new signal to be tracked either immediately or only after the tic has occured if it is desired not to disturb the tracking in effect. 4. load the following preset registers: preset_phase: will set the code dco phase. code_slew: will set the code phase. 1ms_epoch: will set the 1 ms epoch. 20ms_epoch:will set the 20 ms epoch. it is important to have the preset mode selected prior to programming the code_slew and the epoch registers in order to have these new values effective on the next tic as opposed to immediately if they were programmed under up- date mode.the preset_phase register can be programmed either before or after selecting the update mode. in preset mode the value to program in the code_slew register repre- sents the delay between the tic and the first code chip. to ensure correct preset of epoch counters, the loading of preset registers has to be completed prior to the tic relative to which the preset values are computed. thus the operation has to take place within a tic window. it is important to load the 20ms_epoch register last in the loading sequence. the trailing edge of a write to this register enables the preset operation on the next tic. 5. after the preset operation has taken place on a tic, the preset/updb bit of the cntl register is reset and the channel goes back to update mode. it is possible that the code phase has to be slewed so the code_slew register when loaded will then cause a slew to start on the next dump. on the tic, the measurement data saved for the signal being tracked so far will be valid. the measurement data registers (or at least chx_carrier_cycle register) must either be read or a write operation to chx_meas_reset must be made in order to clear the measurement status bits and allow measurement data acquisition on the next tic for the new signal to be tracked under preset mode. 8. the tic generator and the interrupt time base the interrupt time base consists of a free-running counter providing a pulse of constant period on a GP1020 output pin. the frequency uncertainty on this time base will be identical to the system oscillator drift. the interrupt time base shares some dividers with the tic generator. the period of this time base is 175ns 3 2886 = 505.05 m s at power up, but may be changed by programming timer_cntl register, and is always an exact sub-multiple of the tic time base. every 198th (or 18th) interrupt pulse at default rate will occur at the same time as a 100ms (or 9.0909ms) tic, not taking into account propagation delays. either int in or int out (as controlled by the int_source bit of the timer_cntl register) is used to sample and latch the status bits and statistics on incoming sign and magnitude bits. the interrupt is maskable. the int_maskb bit of the timer_cntl register when set low forces the logic level on the output pin to low. a master reset will set this bit low. 9. signal path delay introduced by hardware signal processing the signal path delay has two components as follows: d t = total path delay = d a + d d d a = analogue path delay; varies with temperature and component tolerances. d d = digital path delay; constant if oscillator drift variations are neglected. for gps signals, d d = 125ns. this delay is the time from the sampling edge of the sign and mag bits in the gp1010 (samp clk) to the performance of the correlation in the GP1020 on these same sign and mag bits (100ns) plus the delay between the correlation and the tic clock phases in the master GP1020 (25ns).
GP1020 33 rtc_int at 1 sec rate real time clock clock (43956khz) counter reset enable notes 1. latch counter value saved on tic. 2. register read with measurement data. 100ms tic fig. 17 rtc block diagram microprocessor system rtc_delay GP1020 10. short glitch recovery refer to the block diagram shown in fig. 17 for the following discussion. it is assumed that the rtc selected provides an interrupt output signal which occurs periodically, every 100ms or every second. the interrupt is sent to both the GP1020 and the processor system. within the GP1020, the interrupt is connected to the rtc_int input pin of the GP1020. its edge enables the rtc_delay counter. this counter is clocked by a signal with a period of 2.275 m s and increments until the next tic. the tic causes the value of rtc_delay to be latched in order to be read with the measurement data. when the processor receives the rtc interrupt, it reads the rtc time. alternatively, rtc_tic may not be routed to the processor, but instead, every time the rtc_tic_ack status bit of meas_status_b is set in the GP1020, the software reads the rtc time. with this information, together with the contents of rtc_delay, the software is able to determine first the delay between the rtc and the system clock and secondly, with consecu- tive readings, the rtc drift can be evaluated. these two pieces of information are stored in non-volatile ram every time they are calculated. after occurrence of a power glitch, the 100ms_tic timebase restarts free running but with an arbitrary phase relation- ship with respect to the tics before the power glitch. the rtc interrupt process occurs again as described above and it is possible to relate the new system tic time relative to the previous. ideally, this process is precise enough such that the data bit sync is not lost and all the channel control registers can be reprogrammed with proper values. once the timing relationship is known, the preset mode can be used to resume tracking of the signals. if data bit synchronisation cannot be achieved on a given channel, but proper code and carrier lock are obtained, the software should jump to the data bit synchronisation algorithm. if lock is not obtained, then the software should jump to the search algorithm. given the magnitude of error terms (summed) and the worst case error allowed in order to keep data bit synchronisation, it is possible to calculate the length of the longest permitted power glitch. see fig. 20. 11. time mark generator the time mark generator is designed to provide a one second time mark output signal which can be synchronised with a given time base, such as the receiver time base, the gps time or utc. the time mark is generated after a certain programmable delay relative to the tic. the architecture chosen (see fig. 19) involves minimal hardware being clocked at a high rate and so gives low power consumption. as an example, to synchronise time mark to utc, the software could have the following sequence of operations (see fig. 21): 1. acquire measurement data at time to (on an arbitrary tic) 2. solve for utc at measurement instant utc (t 0 ). note that the solution can only be accurate to within the hardware propa- gation delays in the receiver, typically a few microseconds, unless these delays are calibrated and utc solution is corrected accordingly. 3. compute on which 100ms tic, t m , to take the next sample of measurement data such that: utc time mark 2 t m = d 1 1d 2 rtc_int fig. 18 rtc timing diagram rtc time read here by processor position fix computed on this tic. tic is gps time tagged. 100ms tic rtc_delay d notes 1. d = delay between rtc timebase and system time t s . 2. consecutive measurements of d give an indication of rtc drift. 3. resolution of d is a function of input clock to rtc_delay counter. t s
34 GP1020 where utctime mark = desired time mark synchronised to a utc second. d 1 = k 3 (time between tics), where k=integer and d 1 >nav solution computation delay. d 2 = time offset (with 50 ns resolution) between time mark and 100ms_tic labelled t r d 2 < (time between tics) 4. acquire measurement data at t m compute nav solution at t m propagate nav solution at utc given the oscillator drift, the delay of 25 ns added by time_mark_gen block and the calibrated propagation delay, compute down_count, the value to program into the programmable down counter to delay the time mark by d 2 . 5. program down counter with down_count before the occurrence of t r . 6. output arinc data within 200ms after t r (following arinc 743) 7. locate t m 1 1 and go back to step 4. clock generator 4 571, 428 40mhz masterclock 20-bit programmable down counter 20-bit counter control logic cntl 100ms tic fig. 19 block diagram of time mark generator 4 7 clk markfbx 1 sec. time mark external line drivers GP1020 rtc tic fig. 20 timing diagram of a short glitch 100ms tic d 1 d rtc = (rtc 2 2 rtc 1 2 rtc drift ) notes 1. t s2 = t s1 2 d 1 1d rtc 1 d 2 ( error terms) 2. error terms: in ts 1 : equal to error terms of gps time computation while getting the nav solution in d 1 : can be too long or too short by r, where r = rtc_delay counter clock period in d 2 : same as d 1 in d rtc : residual error in rtc drift estimate, = (effective rtc drift ) 2 (estimated rtc drift ) t s1 t s2 t s3 rtc 1 rtc 2 d 2 nav solution computation delay fig. 21 time mark timing diagram 100ms tic t 0 t r d 1 compute t m d 2 t m time between tics is constant output utc time mark time
GP1020 35 fig. 22 integrated carrier phase measurement tic 0 tic 1 tic 2 y 0 2 p 2 y 0 k 1 cycles d y 1 y 1 k 2 cycles d y 2 y 2 1. reading at tic 0 : 2. reading at tic 1 : 3. reading at tic 2 : chx_carr_dco_phase 0 = y 0 chx_carr_cycle 0 cleared chx_carr_dco_phase 1 =y 1 chx_carr_cycle 1 = k 1 1 1 chx_carr_dco_phase 2 = y 2 chx_carr_cycle 2 = k 2 1 1 d y 1 = 2 p (k 1 1 1) 1 y 1 2 y 0 = 2 p (chx_carr_cycle 1 ) 1 chx_carr_dco_phase 1 2 chx_carr_dco_phase 0 sd y = 2 ps (chx_carr_cycle) 1 chx_carr_dco_phase last 2 chx_carr_dco_phase 0 carrier cycles measurement over more than one tic period utc error budget the following error budget is associated with the generation of the time mark: total error = tdop 1 clock resolution 1 oscillator drift residual error. 1 computation induced error. 1 time mark transfer delay through drivers/cables. 1 propagation delay in hardware, from antenna to correlator to measurement data sampler, where typical values are: 1. tdop : estimated at 177ns with s/a on (2 s number) 2. clock resolution : 50ns (in 21 bit programmable down counter). 3. oscillator drift residual error: (a) due to temperature change on tcxo since last oscillator drift computation: about 50ns, computed with the following assumptions: (i) tcxo max slope is 1 ppm/ c (ii) temperature max variation is 5 c/minute (iii) the oscillator drift is computed every second and is at most one second old at utc time mark. for example: 1ppm/ c 3 5 c/min 3 1sec = 83ns for a temperature step change or 41.5 ns (rounded to 50ns) for a linear ramp (b) due to bias in drift estimation about 50ns max (rough guess) total oscillator drift error = (a) 1 (b) a 100ns. 4. computation induced error: it is assumed that enough significant bits are retained such that this error approximates zero. 5. time mark transfer delay through drivers/cables: this will be calibrated and compensated for up to the gps receivers output using the feedback to the down counter. there will be a residual error due to: (a) clock resolution = 50ns (b) feedback delay calibration = 25ns (estimated) 6. propagation delays in the hardware: these are estimated to be in the range of a few microseconds and are therefore the major contributor to the time mark synchronisation error. an estimate could be included in the software to improve total accuracy when the total hardware design is complete. total = 177ns 1 50ns 1 100ns 1 0 1 75ns 1 hardware delays total = 402ns 1 hardware delays. 12. integrated carrier phase measurement the GP1020 tracking channel hardware allows measure- ment of integrated carrier phase through chx_carr_cycle and chx_carr_dco_phase registers. these two regis ters are part of the measurement data sampled every tic. the first one contains the 16 more significant bits of the number of full cycles elapsed and the second one contains the two remaining less significant bits plus the cycle fraction (phase). fig. 22 shows how to add consecutive readings of these registers over several tics in order to get a consistent integrated carrier phase.
36 GP1020 the next table contains the truth table of the weight converter used in the self_test_generator : carrier_dco bits mag sign (msb-lsb) 01011 1 msb 011xx 1 msb 100xx 1 msb 10100 1 msb all other combinations 0 msb the design of the weight converter will drive a high on the sign bit for 50% of the time and on the mag bit for 31% of the time. examples 1 and 2 show the results of the five first accumula- tions of the accumulated data for two different settings of the self_test_generator and the channels. because the channels had been started at the same time, they are practically in phase with the incoming data (sign and mag outputs of the self_test_generator). 13. built-in test functions a. chip level built-in test functions self_test_generator the GP1020 provides an on-chip self-test pattern generator which is switched on under software control by setting self_test_en bit of the bite register. it uses tracking chan- nel 1 or 2 according to the setting of self_test_source bit of the bite register to generate sign and magnitude -like signals which can be fed back to any or all other channels by selecting the self test signal source in chx_sig_sel. the self- test signal has a fixed data bit pattern of alternating one and zero every 20 milliseconds, the first bit being low. it has a fixed noise pattern which corresponds to particular in-phase and quad- phase accumulated values. the c/a code and the doppler shift can be varied by programming the relevant registers of the channel which has been selected by self_test_source. the standard software can then be used to acquire and track the self-test signal but it should take into account the fact that this self-test signal is not a real gps signal. the self_test_generator output signal can also be wrapped around externally by connecting the tsign and tmag output pins to a gps or glonass input port. normally, the test source and tested channels will have the same dco settings. example 1: register settings value comments (hex) bite 0020 stg on, ch1 as source tdata_duty_cycle 0000 no noise (will cause an overflow condition in q_prompt register if signals are in phase) chx_sig_sel 000a signal from the stg chx_code_incr_hi 016e chx_code_incr_lo a4a8 chx_carr_incr_hi 01f5 chx_carr_incr_lo c28f chx_cntl 0225 sv prn 19, dithering code reset_cntl 007f start all channels at the same time results first second third fourth fifth dump dump dump dump dump chx_i_dith 0388 0318 016c 04cc 02ac chx_q_dith 3d28 3d98 3c34 3d78 3fe4 chx_i_prompt 0a30 093c 0930 08f8 0978 chx_q_prompt 7ffc 7ffc 7ffc 7ffc 7ffc
GP1020 37 scan loops and internal node real-time observability a number of registers are not connected to the data bus in any way. these registers have two modes of operation: the normal mode and the scan loop mode in which the flip flops are cascaded to form a shift register. there is one such scan loop per channel. fig. 23 shows a block diagram of the chip test functions. tdi1 (test data in) is a serial input common to all scan loop shift registers. each scan loop has a separate data o/p pin tdo (1:7) (test data out). the control signal tscan (test scan) determines whether the registers operate in normal mode (tscan low) or in scan loop mode (tscan high). the control signal tcks (test clock select), when high, selects the 7 test clocks tck(1:7) as a replacement for the seven clock phases provided by the clock generator in normal mode. this is intended for use only in the device factory and not in normal operational use. tms1 and tms2 are test mode select control pins. their function is detailed in the following table: tms2 tms1 low low normal mode: sign (2:8) and mag (2:9) configured as inputs. tdo (1:7) held low. tck(1:7) configured as inputs. sign (9) is always used as a normal input. low high scan loop mode: sign (2:8) and mag (2:9) onfigured as inputs. tdo (1:7) output serial scan data. tck (1:7) configured as inputs. high x channel 1 observability mode: sign (2:8), mag (2:9) and tck (1:7) configured as outputs and together with tdo (1:7) allow real-time observability of internal nodes of channel 1 as listed below. the internal tic signal and the signal latching the status bits are also available on tdo4 and tdo7 pins. example 2: register settings value comments (hex) bite 0020 stg on, ch1 as source tdata_duty_cycle 07f7 invert the data 8 times in 11 chx_sig_sel 000a signal from the stg chx_code_incr_hi 016e chx_code_incr_lo a4a8 chx_carr_incr_hi 01f5 chx_carr_incr_lo b1b3 chx_cntl 0315 sv prn 1, early_minus_late code reset_cntl 007f start all channels at the same time results first second third fourth fifth dump dump dump dump dump chx_i_dith 2230 1eb8 2170 2030 1f00 chx_q_dith 0598 0568 0374 078c 03cc chx_i_prompt f8f4 0078 03e8 ff08 0590 chx_q_prompt 46d8 4798 4914 47b8 46d4 add_dat_tst register the add_dat_tst register allows the software and the ate to verify the functionality of the data and address busses. for full details see add_dat_tst section of detailed descrip- tion of registers. b. system-level built-in test functions gp1010 bite interface: the GP1020 bite cntl discrete output is provided to drive the corresponding discrete input pin of the gp1010. when active, this control unlocks the pll and switches off the gp1010 front- end amplifiers. as a result, the GP1020 should read an unlocked status at its pll lock discrete input. the GP1020 includes sign and magnitude statistics checker circuit. glonass ic bite interface: uses the same bite cntl discrete output to put the glonass ic into test mode and one GP1020 discrete input pin, glonassbit, for glonass ic go/nogo status. time mark : three mark feedback input pins, selected by bits 7 to 5 of timer_cntl, are provided for testing the signal outputs of time mark line drivers. also, software selectable control bits (timer_cntl bits 4 and 8) allow multiplexing of the normal 1 second period time mark with one of two test signals, either 40mhz/91 = 439.5604khz intended for oscillator drift measurement or ch1_dump for system fault-finding purposes. 14. chip manufacturing-test functions the GP1020 design incorporates a series of features to increase (a) the observability of internal nodes when working in the application and ( b) the observability and the controllability of the circuit during chip-level testing during manufacture. the following presents a summary of the chip test functions: test registers a number of registers have been added to improve the testability of the chip. they are not required for normal operation : chx_tst_code_phase, chx_tst_cycle and chx_tst_code_slew.
38 GP1020 other chip functions channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 cntl mux tdi 1 tck 8 tscan serial data nodes mux cntl mux cntl mux cntl mux cntl mux cntl mux cntl mux cntl clock generator tms 2 sign (2 : 8) mag (2 : 9) tdo (1) tdo (2) tdo (3) tdo (4) tdo (5) tdo (6) tdo (7) tms1 tcks tck (1 : 7) tcks clk (1 : 7) clk (1 : 7) fig. 23 chip test functions
GP1020 39 table of accessible channel internal nodes prompt bit 0 bit 1 bit 2 bit 3 tck3 tck4 tck5 tck6 cntl pin: tms1: cntl pin: sign9 o/p pin sign 2 mag 2 sign 3 mag 3 sign4 mag 4 sign 5 low low prompt bit 13 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 high low dithering 13 11 10 9 8 7 6 low high prompt 12 5 4 3 2 1 0 low high dithering 12 5 4 3 2 1 0 in phase i & q accumulator arm mag 5 sign 6 mag 6 sign 7 mag 7 sign 8 mag 8 mag 9 prompt bit 13 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 dump dithering 13 11 10 9 8 7 6 dump dithering 12 5 4 3 2 1 0 dump quad-phase i & q accumulator arm prompt 12 5 4 3 2 1 0 dump mix_correl output dithering 0 1 2 3 dithering 0 1 2 3 in phase arm prompt 0 1 2 3 quad phase arm cntl pin: tms1: cntl pin: sign9 tdo1 tdo2 tdo3 tdo4 tdo5 tdo6 tdo7 codeclk prompt c/a code preset load tic carr dco o/p bit 27 1ms epoch carry status latch control code clk dithering c/a code carr dco o/p bit 25 carr dco o/p bit 26 carr dco o/p bit 27 1ms epoch carry status latch control low x high x cntl pin: tms1: cntl pin: sign9 tck1 tck2 tck7 sampled sign sampled mag rescodegen x x
40 GP1020 15. boundary scan loop a boundary scan loop is implemented to allow the ate to verify the connections of the chip at board level. the following pins are not included in boundary scan loop : tdi1 100/219khz sampclk masterclk bias plllockin slaveclk tck(1:8) mark rtcint markfb1 markfb2 markfb3 nanda nandb nandop the tap controller has all functions necessary to be compatible with the jtag standard (ieee 1149.1-1990) with a few exceptions : all bidirectional pins are in input mode when the trst signal is inactive (high) so the chip cannot run freely when in bypass mode. the capture-ir state loads the instruction 000 instead of x01. the pins tms, tck and trst do not have pull-up resistors. this is the order of the pins in the loop (column by column): a7 a8 master/ slave tcks masterreset mot/ intel cs wen rw tms2 tms1 tmag * tsign * mag2 intout * sign2 mag3 sign3 mag4 sign4 mag5 sign5 mag6 sign6 mag7 sign7 mag8 sign8 mag9 sign9 mag1 sign1 mag0 sign0 clksel bitecntl * glonassbit intin ticin ticout * d0 d1 d2 d3 d4 d5 d6 d7 wprog d8 d9 d10 d11 d12 d13 d14 d15 ale a1 a2 a3 a4 a5 a6 tscan note: an asterisk in the above list indicates an output pin.
GP1020 41 application notes pcb layout considerations the GP1020 is a fast cmos device so, although clock rates are low, the edge speeds can be very high. the board layout must, therefore, handle these edges on both output signals and on power supply current. simplified system it is not always necessary to use all of the features of the GP1020 to make a good gps receiver. the following pin connections show the minimum requirement and are given as a guide only. unused inputs must be tied to v ss or v dd and not left floating. failure to observe this may result in malfunction or damage to the device. pin no. 1 and 2 3 4 and 5 6 7 8 9 10 11 12 13 14 and 15 16 and17 18 19 20 21 22 23 to 39 40 41 42 and 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 to 65 66 67 68 and 69 70 71 72 and 73 74 75 76 and 77 78 and 79 80 signal name a7, a8 master/ slave tscan, tcks tdi1 masterreset mot/ intel cs v ss v dd wen rw tms2, tms1 tmag, tsign mag2 100/219khz v dd v ss intout sign and mag 1 to 9 v ss v dd mag0, sign0 sampclk v dd masterclk v ss bias v ss v dd v ss clksel plllockin bitecntl glonassbit slaveclk intin tck 1to 8 ticin ticout d0 and d1 v ss v dd d2 and d3 timemark rtcint markfb 1 and 2 d4 and d5 v dd description address bus master or slave mode select control test mode test data serial input general reset, active low bus mode select chip select, active low ground positive supply write enable - see mode table, page 3 read/write - see mode table, page 3 test mode select 2 and 1 test prn pattern output source 2 mag input clock output positive supply ground interrupt output source 1 to 9 sign and mag inputs ground positive supply source mag and sign inputs sampling clock positive supply 40mhz master clock ground bias for master clock ground positive supply ground 100khz (high)/219khz (low) select pll status input bite control to front-end glonass bite input master to slave clock interrupt input for slave test clocks or signals tic input to slave tic output from master data bus ground positive supply data bus 1 pps output real time clock interrupt input time mark driver feedback data bus positive supply connection to microprocessor high, unless slave both low low power-on timer high for motorola, low for intel to microprocessor 0v 1 5v to microprocessor to microprocessor both low leave open low leave open 1 5v 0v to microprocessor all low 0v 1 5v to gp1010 to gp1010 1 5v to gp1010 0v see fig. 12 (page 8) 0v 1 5v 0v high low or gp1010 leave open low leave open low all low low leave open to microprocessor 0v 1 5v to microprocessor leave open low both low to microprocessor 1 5v continued
42 GP1020 pin connections for a simplified system (continued) pin no. 81 82 and 83 84 85 and 86 87 88 and 89 90 91 and 92 93 94 95 96 and 97 98 and 99 100 101 102 and 103 104 to 107 108 and 109 110 111 112 and 113 114 115 to 120 connection 0v to microprocessor low (see note 5) low leave open both low leave open both low low leave open leave open leave open to microprocessor 0v 1 5v to microprocessor leave open to microprocessor 1 5v 0v to microprocessor to microprocessor to microprocessor description ground data bus bus timing mode select test/spare gate inputs boundary scan output boundary scan clock and reset test/spare gate output boundary scan select and input time mark driver feedback test data output 7 general purpose output pin test data outputs 6 and 5 data bus ground positive supply data bus test data outputs 4 to 1 data bus positive supply ground data bus address latch enable address bus signal name v ss d6 and d7 wprog nanda and b tdo tck and trst nandop tms and tdi markfb3 tdo7 discop tdo6 and tdo5 d8 and d9 v ss v dd d10 and d11 tdo4 to tdo1 d12 and d13 v dd v ss d14 and d15 ale a1 to a6 notes 1. the action of wen and rw is given in the table at the foot of page 3. 2. in the above list, it is assumed that only one front-end is being used and that it is connected to sign0 and mag0. any other sign and mag pair may be chosen if desired. 3. unused inputs are listed in the above table as tied low (to ground) so that they are not left floating. 4. connections listed ?to microprocessor? may, in some systems, be made via glue logic such as address latches. 5. wprog is used to modify the write timing. for most applications, wprog should be tied low. for use with an intel 486, it may be better to tie wprog high to delay the start of the write operation until after the address decode in the GP1020 has settled. 6. ale is listed as ?to microprocessor? but it is possible in systems with wprog tied low to have ale tied high to make the latches in the GP1020 transparent if the address bus is externally latched for the write or read operation.

www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of GP1020

	To Download GP1020 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .